STARCHIP develops a High-performance 32-bit RISC Secure core based on CORTUS APS3s CPU
Announcement is a step further in confirming StarChips strategic commitment to the Smart Card business by extending its product portfolio into payment and ID markets.
MEYREUIL, April 12th, 2012 - StarChip®, experts in designing and qualifying Smart Card ICs announced today the development of the ARX (Fortress in Latin). The ARX CPU is a High-performance 32-bit RISC Secure Core based on Cortus APS3s CPU. This announcement is a step further to confirm StarChip®s strategic commitment to Smart Card business by extending its product portfolio to payment and ID markets.
To develop their Secure Core, StarChip® selected the APS3s from Cortus. The APS3s is a full 32-bit general purpose CPU specifically designed to meet the requirements of embedded systems.
The APS family are modern RISC processors with Harvard architecture. They feature leading code density and high power efficiency yet also very high performance.
In addition to these state-of-the-art technical features StarChip® and Cortus have signed an agreement allowing StarChip to augment the design of the APS3s to implement embedded security mechanisms. This is the starting point for StarChip® to implement its innovative strategy GAIA: A new vision of self healing security architecture on silicon. As a result the StarChip® Secure Core will embed all the necessary technology to counter both Side-Channel attacks and Fault Injection attacks making it ideal for applications requiring the highest levels of security.
The ARX CPU development is the key to having unsecured software algorithms running in a fully secure way on a CPU without adding costly software counter-measures.
We have verified the quality and the efficiency of the Cortus APS3s core from our experience in the SIM controller market, said Yves Fusella, CTO of StarChip®. Having an agreement between StarChip® & Cortus to modify the APS3s was also a key element in our decision of choosing the APS3 as a starting point for the ARX core. It allows the StarChip® team to use the best design practices and to implement state-of-the-art and innovative security mechanisms while optimizing the overall gate count of the CPU.
We are very enthusiastic about this development. StarChip® are showing what can be done with our processor IP and tool chain. Not only does the APS3s offer excellent performance, very low power and a tiny footprint; it is also highly configurable and perfectly corresponds to the needs of chip card security systems. This demonstrates the wide range of applications of our processor cores, from these security systems through wireless metering and to powerful multi-core controllers. said Michael Chapman, President and CEO of Cortus.
About StarChip®: (www.starchip-ic.com)
StarChip® is a dynamic semiconductor company that enables customers to directly benefit from our unique, optimized value chain system. We design and qualify products for mass production, then license our solutions for purchase directly by our customers through qualified foundries and test houses.
StarChip® products are based on state-of-the art, Flash-based 32-bit architectures. They are designed to offer maximum integration, providing support for embedded, innovative security technologies, analog functionality and connectivity and control interfaces. The result is a flexible set of solutions that can easily meet the requirements of a wide variety of markets, including smart cards and security, consumer, automotive and industrial applications.
Cortus is committed to providing high-performance 32-bit processor IP and the surrounding IP and tools. Cortus is a private French company founded in Montpellier in the south of France.
Cortus family of processor IP has been used in a wide variety of products ranging from Pay TV access cards to Cameras and Mobile Phones.
Cortus aim is to "Provide a better CPU for low cost embedded systems".
The team has many years experience in multinational companies (Intel, Bosch, Infineon, Siemens, Synopsys), and is composed experts in processor design.