Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Dresden, GERMANY – February 4, 2013 –Technische Universität (TU) Dresden, a leading German university in the field of electrical engineering, today announced the successful initial operation of a low-power test-chip featuring a Tensilica Xtensa LX4 DSP equipped with RacyICs power management IP implemented in GLOBALFOUNDRIES’ advanced 28nm Super Low Power (SLP) technology. The chip is able to operate in a wide voltage and frequency range from 0.7V to 1.1V and 90 MHz to 1 GHz. Within that range, the optimal voltage/frequency combination is determined adaptively based on a new hardware performance monitor concept. The complete baseline IP (standard cell libraries, IO cells, SRAM blocks, PLL) was developed by the university team, who also did logic synthesis, place and route and sign-off of the test-chip.
“Our ability to successfully realize microchips in advanced technologies is a result of a long- term strategy to build an experienced team, which covers all aspects of analog, digital and mixed-signal IC design.” stated Professor René Schüffny, TU Dresden. “This accumulated engineering competence is one key enabler for TU Dresden’s leading-edge research in the field of complex systems based on advanced electronics.”
The chip has been developed within the frame of the CoolRF28 project. This project is part of the Leading-Edge Cluster “Cool Silicon”, which is sponsored by the German Federal Ministry of Education and Research (BMBF) within the scope of its Leading-Edge Cluster Competition. In the “Cool Silicon” cluster, universities, research institutes, small and medium enterprises (SMEs) and big corporations closely cooperate in numerous projects on the next generation of energy-efficient electronics.
“We’re very impressed by the high research and engineering competence of the TU Dresden team,” stated Frank Dresig, GLOBALFOUNDRIES’ European Field Engineering Manager. “The chip directly shows the capabilities of our advanced 28nm SLP process for implementation of ultra low-power SoCs for consumer applications.”
The test-chip’s power management is based on an IP for adaptive voltage and frequency scaling provided by RacyICs, a start-up company offering design and implementation services.
“The close cooperation with TU Dresden and GLOBALFOUNDRIES helps us to develop world-class services and IP products in advanced technology nodes,” stated Holger Eisenreich, RacyICs’ Managing Director. “Because of high risks and costs, it is almost impossible for SMEs to enter this market without such cooperation.”
With assistance from Tensilica, the university team integrated an Xtensa LX4 DSP core to demonstrate the overall power reduction benefits from the combination of a 28nm low power technology, adaptive power management and an advanced processor IP core.
"Tensilica has had a long-standing relationship with the researchers at TU Dresden and congratulates them on this successful design effort," stated Chris Rowen, Tensilca's CTO. "Tensilica's Xtensa processor is a fundamental building block in TU Dresden's wireless communications architecture, and we are working together to proliferate know-how on configurable architectures to the worldwide design community."
About Technische Universität Dresden
Founded in 1828, Technische Universität Dresden (TU Dresden) is a full-scale university with 14 faculties, covering a wide range of fields in science and engineering, humanities, social sciences and medicine. TU Dresden has about 36,500 students and almost 5,319 employees with 507 professors among them, and thus is the largest university in Saxony today. Since June 2012 TU Dresden is one of eleven German universities that were identified as "excellence universities". One of the strategic research directions are driven within the Clusters of Excellence, Center for Advancing Electronics Dresden (cfAED). Furthermore, TU Dresden's emphasis on applications in both teaching and research has been honored by leading industrial companies with currently fourteen endowed chairs.
RacyICs GmbH offers SoC design, verification and implementation services in leading edge CMOS-technologies down to 28nm feature size. RacyICs addresses low power requirements of these systems by providing concepts and IP for advanced on-chip power management features and by application of innovative power analysis and optimization methodologies during design stage. For more information, visit www.racyics.com.
Tensilica, Inc. is the leader in dataplane processor IP cores, with over 200 licensees. Dataplane processors (DPUs) combine the best capabilities of DSPs and CPUs while delivering 10 to 100x the performance because they can be optimized using Tensilica’s automated design tools to meet specific and demanding signal processing performance targets. Tensilica’s DPUs power SOC designs at system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. Tensilica offers standard cores and hardware/software solutions that can be used as is or easily customized by semiconductor companies and OEMs for added differentiation. For more information on Tensilica’s patented, benchmark-proven DPUs visit www.tensilica.com.