IP core manages SoC memory bandwidth
IP core manages SoC memory bandwidth
By Nicolas Mokhoff, EE Times
June 4, 2002 (1:16 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020604S0017
>NEW YORK Denali Software Inc. has enhanced its Databahn memory controller intellectual property (IP) core by adding an ability to regulate and optimize memory bandwidth in a system-on-chip (SoC) design. The core can now manage the memory access of multiple on-chip computing clients to the finite bandwidth of off-chip DRAM.
SoCs usually require high-bandwidth access to off-chip memory, and access that memory in two ways: via an on-chip bus like Amba; or via dedicated ports. Sonics Inc., another IP provider, offers a core that manages memory access to on-chip buses. Denali's enhanced Databahn core accommodates the Amba bus and proprietary buses. The Denali core enables designers to optimize an SoC's memory controller configurations without matching the bandwidth and latency requirements of individual processing units with memory, and without readjusting the memory access to pro cessing elements when trying to support new memory types, the company said.
"Databahn resolves all of these conflicting requirements," said Mark Gogolewski, chief operating officer and vice president of engineering at Denali Software. "This new Databahn core contains a completely configurable multi-port arbitration unit, integrated to a configurable DRAM memory controller."
The solution allows dynamic and granular trade-offs between high-priority, low-latency requests and overall optimized bandwidth. Furthermore, Databahn is supported by online performance analysis tools at the eMemory.com Web site, where system architects can prove out their SoC approach with a variety of the DRAM types.
The Databahn core supports more than 4,500 different memory components, including the latest DDR-SDRAM, FCRAM and RLDRAM, the company said.
|
Related News
- Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing and Networking Applications and Showcase its IoT Gateway SoC Reference Design for Smart City Applications at ARM TechCon 2017
- Revolutionary New Databahn Core Solves Memory Bandwidth Bottleneck for SoC Designs
- Mobiveil's PSRAM Controller IP Lets SoC Designers Leverage AP Memory's Xccela x8/x16 250 MHz PSRAM Memory
- JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard
- Xilinx Versal HBM Series with Integrated High Bandwidth Memory Tackles Big Data Compute Challenges in the Network and Cloud
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |