October 31, 2013 -- Digital Core Design, IP Core provider and the System on Chip design house from Poland introduced in its offer the D8259. DCDs Programmable Interrupt Controller is fully compatible with the 82C59A device. As all other cores design by Polish company, the D8259 is tech-nology independent, so it can be implemented both in ASIC and FPGA.
The D8259 is a soft Core of Programmable Interrupt Controller, which is fully compatible with the 82C59A device. DCDs IP core can manage up to 8-vectored priority interrupts for the processor. But thats not all, cause you can also program it to cascade and gain up to 64 vectored interrupts - adds Jacek Hanke, DCDs CEO. And if it still seems to be not enough, one can always get more than 64 vectored interrupts, by programming the D8259 to the Poll Command Mode.
The D8259 Package includes fully automated testbench. Thanks to complete set of tests, one can easily validate the whole package at each stage of SoC design flow. Same as all other DCD's IP Cores, this one's got also a technology independent design, that can be implemented in a variety of process technologies.
The D8259 can operate in all 82C59A modes and it supports all 82C59A features:
- MCS80/85 and 8088/8086 processor modes
- Fully nested mode and special fully nested mode
- Special mask mode
- Buffered mode
- Pool command mode
- Cascade mode with master or slave selection
- Automatic end of interrupt mode
- Specific and non specific end of interrupt commands
- Automatic and Specific Rotation
- Edge and level triggered interrupt input modes
- Reading of interrupt request register (IIR) and in service register (ISR) through data bus.
- Writing and reading of interrupt mask register (IMR) through data bus
More information about D8259 IP Core: http://dcd.pl/ipcore/134/d8259/