Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
Delivers Higher Frequency and Smaller Area Compared to Other Synthesis Solutions
MOUNTAIN VIEW, Calif., July 6, 2015 -- Synopsys, Inc. (Nasdaq: SNPS), today announced that Key ASIC, a leading supplier of wireless storage solutions and a design and manufacturing service provider specializing in customer-specific system products (CSSPs) and high-performance, low-power ASICs, has deployed the Synopsys Design Compiler® Graphical RTL synthesis solution to accelerate system-on-chip (SoC) design. Achieving high performance, low power and small die size results are primary objectives for Key ASIC to enable quick and cost-effective tapeouts. After a comprehensive evaluation of available synthesis solutions, Key ASIC found the most appropriate tool combination for their design needs is Design Compiler Graphical and Synopsys' IC Compiler™ place-and-route solution, which consistently deliver better timing QoR and smaller area.
"Key ASIC's design expertise targets the critical challenges of smaller die size, functional integration and cost reduction for high-performance, low-power SoCs," said Meisie Jong, general manager of Key ASIC's Technology Services business unit. "With Design Compiler Graphical we can identify and fix timing issues in a timely manner during synthesis and achieve higher frequency and smaller area faster. Based on our evaluation experience, we have now deployed Design Compiler Graphical as part of our production design flow."
Design Compiler Graphical addresses challenging requirements, such as performance, area, power and congestion, at both established and emerging process nodes. It provides IC designers with visualization of congested circuit regions and performs automated synthesis optimizations to minimize congestion in these areas. Additionally, new optimization technologies monotonically reduce design area and leakage power by an average of 20 percent while maintaining timing QoR. Design Compiler Graphical shares physical technologies with Synopsys' IC Compiler and IC Compiler II place-and-route solutions to deliver highly correlated results for timing, area, power and routability, reducing design iterations and shaving critical schedule time.
"Key ASIC's solutions and the customers they serve require the best combination of performance, low power and small die size to be competitive and cost-effective in the market," said Bijan Kiani, vice president of marketing in Synopsys' Design Group. "Design Compiler Graphical's market-leading synthesis technologies and tight correlation with IC Compiler enable Key ASIC to focus on their design expertise and unique IP while achieving the best quality of results and reduced tapeout schedules."
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot Verification IP
Related News
- Avnet ASIC Israel Ltd. (AAI) Standardizes on Synopsys' Design Compiler Graphical to Accelerate SoC Design Cycle
- Samsung Widely Deploys Synopsys' Design Compiler Graphical for Mobile SoC Designs
- Achronix Tapes Out Industry's First FinFET-based System-on-Chip Using Synopsys' IC Compiler and IC Validator
- Synopsys Introduces 3DIC Compiler, Industry's First Unified Platform to Accelerate Multi-die System Design and Integration
- Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |