Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores with Superfast speed and High-power efficiency for lag-less data processing is Silicon Proven and available in 8nm LPP for licensing
29th November 21 – T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores in 8nm LPP process node which is silicon proven in major Fabs and in mass production with full certification, greatly increased power efficiency and decreased logic area compared to higher nodes.
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores consist of Universal Serial Bus (USB) compliant with the USB 3.0 (USB High-speed and Full speed), Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of PIPE interface spec, and Serial ATA (SATA) compliant with SATA 3.0 Specification. Due to the architecture of the 8nm LPP process node, lower power consumption is achieved along with support of additional PLL control and reference clock control. The high level of control allowed in the PHY also makes the Combo PHY reliable and effective in different power consumption levels.
Compatible with PCIe2/USB3/SATA3 base Specification and fully compatible with PIPE3.1 interface specification the USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP Cores can achieve a data rate configurable to 1.25G/1.5G/2.5G/3G/5G/6G for different application. It supports 16-bit or 32-bit parallel interface when encode/decode enabled and 20-bit parallel interface when encode/decode is bypassed. Spread-Spectrum clock (SSC) generation and receiving from -5000ppm to 0ppm makes it flexible along with programmable transmit amplitude.
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP cores in 8LPP has PCIe Mode that supports 100MHz differential reference clock input or output (optional with SSC) and Beacon signal generation and detection. USB3.0 Mode supports Low Frequency Periodic Signalling (LFPS) generation and detection. SATA Mode supports COMWAKE, COMINIT and COMRESET (OOB) generation and detection along with RX low latency mode. These with added benefit of process node allows L1 sub-state power management.
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP cores have been used in semiconductor industry’s Cellular Electronics, PC, Data storage (SSDs), Multimedia Devices, Servers, Cryptocurrency and other Consumer Electronics …
In addition to USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP cores, T2M ‘s broad silicon Interface IP Cores Portfolio includes Standalone USB, PCIe, Serial ATA and also HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 5nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com
|
T2M Hot IP
- Bluetooth Dual Mode v5.4 / IEEE 15.4 PHY/RF IP in TSMC22nm ULP
- GNSS Ultra low power (GPS, Galileo, GLONASS, Beidou3, QZSS, IRNSS, SBAS) Digital ...
- USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
- DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
- MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
Related News
- USB 4.0, USB 3.2, USB 3.0, USB 2.0 Silicon Proven PHYs in TSMC, UMC & SMIC Foundries available from T2MIP
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP Cores for High Bandwidth, Low Power data communication in PCs, Mobiles, SSDs, and other Multimedia Devices.
- Unveiling Silicon-proven USB 3.0 PHY IP Core in 22nm, Elevating High-Speed Data Transmission with Advanced Transceiver Technology, backward compatible with USB 2.0
- Enhance your High-Density data processing capabilities to new heights with the USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP Core interface in 28HPC+/HPC process technology
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 12nm, 16nm and 22nm process nodes with simple integration and flexible customization is ready for immediate licencing for your advanced SoC design
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |