Imperas releases new RISC-V verification product that changes the fabric of processor DV

With a combined 100 years of experience and 10 years of effort creates new ImperasDV killer-app for RISC-V verification engineers

Oxford, United Kingdom, December 6^th, 2021 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced ImperasDV^TM as the integrated solution for RISC-V processor verification. RISC-V is an open standard ISA (Instruction Set Architecture) that allows any SoC developer to design and extend a custom processor, while remaining compatible with the growing ecosystem of supporting tools and software. The innovation and impact of RISC-V on the design side is driving new developments across all segments and applications of the semiconductor market. Now, with ImperasDV, SoC developers have a dependable, reference model-based solution for verification that is compatible with the current UVM SystemVerilog methods for SoC verification.

Currently SoC verification is estimated to be 50-80% of the total design time and cost. With the success of the semiconductor IP business model, these verification estimates do not include the processor IP, since the base assumption is these specialist suppliers provide a pre-tested building block of sufficient quality. With RISC-V, since any SoC team can now undertake the design freedom to implement a custom processor, optimized to the unique application requirements, they also assume responsibility for the extra complexity of processor verification. As a guide to the scale of the DV task, on average a processor core can be 10x the complexity of the SoC that is developed around it.

Due to the wide range of configuration options within the RISC-V specifications, the verification task has previously required extensive set-up and time-consuming manual adjustments to the established SoC design and verification flow. This is especially the case when custom extensions or modifications are included during the design, which are often iterated with the common HW/SW co-design as the software driven design style explores additional custom feature optimizations. The increasing popularity of open-source IP is also contributing to the growth in teams undertaking verification as an in-coming quality inspection as part of initial phase of an SoC project, plus the design option to modify or extend the base core functionality will depend on a working DV framework from the start.

ImperasDV is created as a solution for easy, high quality processor verification adoption within the established SoC Design Verification (DV) flows based on UVM and SystemVerilog. The key components are: Imperas RISC-V golden reference model, integrated test bench components, test suites, plus professional support and training.

ImperasDV – The integrated solution for RISC-V processor verification

• Imperas RISC-V golden reference model
  • Envelope model covers the entire RISC-V ISA including privileged mode
  • Supports the latest extensions for
    • Crypto (Scalar), Bitmanip, Vector, and DSP/SIMD
  • Configurable support for previous specification revisions and drafts
  • Supports user defined custom instructions and extensions
• Integrated testbench components
  • SystemVerilog components compatible with all major EDA environments
  • C/C++ components for use in C/C++ test benches using Verilator
  • New open standard RVVI (RISC-V Verification Interface) provides:
    • Seamless integration between RTL, reference model and testbench
    • Close-coupled integration for instruction accurate step-and-compare
    • Supports multi-hart, superscalar and out-of-order CPU pipelines
  • Verification coverage with instruction level analysis and reporting
• Test suites
  • Supports multiple options for popular ISG (Instruction Stream Generators)
    • RISCV-DV open source ISG developed by the team at Google
    • FORCE-RISCV open source ISG maintained by the OpenHW Group
  • The Valtrix Systems STING test generator supports pre-integrated Imperas RISC-V reference models to generate portable bare-metal programs containing self-checking architecturally-correct test stimulus
  • Imperas Architectural reference test suites including Floating Point, Bitmanip, Crypto, Vector, DSP/SIMD
  • RISC-V International architectural compatibility test suites
• Product support and training
  • As a commercial product all design information remains with the user
  • Imperas technical support available worldwide
  • Imperas technical training available in-person or via virtual meetings

The latest RISC-V verification ‘step-and-compare’ methodology can be used to verify an RTL processor implementation against the Imperas golden reference model encapsulated within a SystemVerilog UVM environment. This covers asynchronous events and offers a seamless, time-saving, transition to debug analysis when an issue is found. More details on test benches with Imperas RISC-V verification reference models are available at https://www.imperas.com/riscv. ImperasDV can also be used with the popular open source Verilator and C/C++ test benches.

The new RVVI (RISC-V Verification Interface) is an open standard developed by Imperas with guidance and support from lead customers and users, and is available for the RISC-V test and verification community at https://github.com/riscv-verification/RVVI.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on 2^nd generation designs. These customers, partners and users span the breadth of RISC-V adopters from open source to commercial; research to industrial; microcontrollers to high performance computing. A select sample of these include - Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems, plus many others yet to be made public.

“RISC-V is ideal for the latest compute requirements of single-core embedded controllers through to multicore arrays for high performance computing applications,” said Calista Redmond, CEO of RISC-V International. “Companies like Imperas are leading the charge in making SoC design and verification flow easier to further accelerate the mass adoption of RISC-V.”

“The open ISA of RISC-V is at the forefront of the wave of innovation that is stimulating design exploration across all embedded and compute markets,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V offers SoC develops the design freedoms for a custom processor as a unique solution optimized at the point of use, however this shifts the verification task from the few specialist suppliers to all SoC teams. Our new product, ImperasDV provides the efficiency and trusted quality for SoC teams as they step-up to the challenge of RISC‑V verification, which represents the greatest migration in verification responsibility in the history of EDA.”

Availability

ImperasDV is available now, more details are available at Imperas.com/ImperasDV.

The free riscvOVPsimPlus package, including the test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

RISC-V Summit 2021

The RISC-V Summit and DAC are co-located for 2021, running December 6-8 in San Francisco, CA.

Imperas is a Diamond Sponsor for the RISC-V Summit 2021; more details on all the keynotes, talks and to request a demo are available at this link.

About Imperas

Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.