SEGGER licenses C++ runtime library to SiFive for code size and performance efficiency
September 29, 2022 -- SEGGER, a leading supplier of RTOS and software libraries, debug and trace probes, in-system flash programmers, and software development tools, is proud to announce that SiFive, Inc., the founder and leader of RISC-V computing, has licensed SEGGER’s cutting-edge emRun++ C++ library for RISC-V.
emRun++ is a complete C++ standard library specifically designed and optimized for GCC/LLVM-based toolchains and embedded systems. It is based on SEGGER's efficient emRun and emFloat runtime and floating-point libraries.
Ad |
High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP RISC-V processor - 32 bit, 5-stage pipeline 32-bit Embedded RISC-V Functional Safety Processor |
“After licensing and integrating SEGGER’s emRun C runtime library for RISC-V into our Freedom Studio IDE and Freedom Tools packages in 2021, and experiencing its superior code size and performance compared to existing open-source alternatives, the next step was to consider C++ support. It was an easy decision to upgrade to emRun++ once it became available for licensing,” said Sam Grove, Director of Product Management — Software at SiFive. “As a modern programming language, C++ has become increasingly important in the embedded sector, offering developers more and more options. It is essential for SiFive to be able to offer a state-of-the-art C++ library to our customers. emRun++ is perfectly suited for this purpose.”
“SEGGER’s emRun++ is a proven part of our multi-platform Embedded Studio IDE. The memory footprint and the performance are simply amazing,” says Rolf Segger, founder of SEGGER. “SiFive customers have already been enjoying the benefits of the SEGGER emRun C library, and soon, C++ developers using SiFive tools will also benefit from emRun++.”
emRun++ guarantees fast heap operations with a low instruction count, enabling even hard real-time applications to be written in C++. To support common embedded use cases even on resource-constrained targets, the C++ library is available in a “no-throw” configuration, avoiding overhead associated with exceptions.
Designed specifically for embedded systems, emRun++ provides interrupt-safe memory management, allowing use of C++ in Interrupt Service Routines.
emRun++ includes a complete C++17 Standard Library with standard algorithms (sorting, searching, transformations), generic container templates (such as sets, vectors, lists, queues, stacks, maps), function objects, iterators, localization, strings and streams, and utility functions for everyday use cases.
For more information on emRun++, please visit:
https://www.segger.com/products/development-tools/emrunpp/
|
Related News
- SEGGER's emRun Runtime Library Licensed by SiFive for Superior Code Size and Performance Improvements
- IAR Systems takes RISC-V to the next level with launch of professional development tools with leading performance and ensured code quality
- Sophgo Licenses SiFive RISC-V Processor Cores to Drive High-Performance AI Computing Innovation
- SiFive Announces Differentiated Solutions for Generative AI and ML Applications Leading RISC-V into a New Era of High-Performance Innovation
- SiFive Rolls Out Powerful New RISC-V Portfolio to Address Unmet Performance and Feature Needs of Rapidly Evolving Next-Gen Digital Automobiles
Breaking News
- Alphawave Semi announced today a refocussing of the Board of Directors after reaching the three-year milestone since the Company's IPO
- Synopsys and Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU with Leading Performance on Samsung Foundry's GAA Process
- Worldwide Silicon Wafer Shipments Dip 5% in Q1 2024, SEMI Reports
- GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment
- PCI-SIG® Announces CopprLink™ Cable Specifications for PCIe® 5.0 and 6.0 Technology
Most Popular
- Silvaco Announces Launch of Initial Public Offering
- TSMC's A16 Process Moves Goalposts in Tech-Leadership Game
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- QuickLogic Releases Aurora 2.6 with Expanded Operating System Support and Up to 15% Faster Performance
E-mail This Article | Printer-Friendly Page |