DDR5/DDR4/LPDDR5 Combo PHY IP Cores which is Silicon Proven in 12FFC with Matching Controller IP Cores is available for license to accelerate your Memory Interfacing Speeds

November 9, 2022 - T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s DDR5/DDR4/LPDDR5 Combo PHY IP Cores in 12FFC process nodes with matching DDR5 Combo Controller IP Cores which are silicon proven and has been extracted from production chips.

The DDR5/DDR4/LPDDR5 Combo PHY IP Cores' hierarchical yet comprehensible design enables simple integration into any design architecture, offers minimal latency, and supports throughput of up to 5400MT/s. Programmable output impedance (DS) and Programmable on-die termination are available as unique features (ODT). The DDR5 Combo PHY IP Cores with matching Controller can support up to 16 AXI ports with data width up to 512 bits and is compliant with DFI version 5.0 Specification.

The DDR5/DDR4/LPDDR5 Combo PHY IP Cores may also function independently in DDR4, DDR5, and LPDDR5 modes. With maximum controller clock frequencies of 675MHz, 400MHz, and 600MHz, respectively, this process technology supports a variety of standards, including DDR5, DDR4, and LPDDR5, with maximum DRAM data rates of 5400MT/s for DDR5, 3200MT/s for DDR4, and 4800MT/s for LPDDR5. It supports CA/DQ X16/DQ X8/ZQ and four more modules for versatile setup. The ZQ calibration function and support for 4 ranks by each CA module in various considerations of power usage are additional innovations of the 12FFC technology.

The detailed, user-friendly, and programmable DDR5/DDR4/LPDDR5 Combo Controller IP Cores are compliant with DDR5 JESD79-5 and JESD79-5 standard. Different clock frequencies for DDR5, DDR4, and LPDDR5 are compatible with it. Additional features include Maximum Power Saving Mode (MPSM), Precharge Command modes, Error Checking and Correction (ECC), reordering of transactions for better performance, Self-Refresh, and Power Down operation. It also allows PHY internal auto decision. It can support device densities of up to 64GB and X4, X8, and X16 device formats.

The DDR5 Combo PHY IP Cores along with the DDR5 Combo Controller IP Cores has been used in semiconductor industry’s Enterprise computing, storage area networks, Embedded systems, Graphics devices and other Consumer Electronics...

In addition to DDR5 IP Cores, T2M ‘s broad silicon Interface IP Cores Portfolio includes USB, HDMI, Display Port,, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, 1G Ethernet, V-by-One, programmable SerDes, SD/eMMCs, Serial ATA and many more IP Cores, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

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