Analysis: Choice of ASIC gate width can be boon to design

The change embodied in the company's Matrix ASICs involves the dimensions of transistors. Normally the realm of cell library developers and analog designers, transistor models explain how the behavior of a device changes with the channel length, L, and width (perversely called H here, not W). This is vital stuff if you are scaling transistors for an analog circuit. But it is entirely concealed from digital designers, except for one point: L, for historical reasons, has been chosen as the naming convention for process nodes. So discussion of 130-nanometer processes, for example, is discussion of processes in which the minimum intended drawn gate length is 130 nm.

Decreasing L is one of the contributing factors in the growing problem of transistor incontinence. When designers make transistors faster (and cells denser, in some cases) by shrinking L, they also increase the subthreshold leakage. This problem has begun to impact design flows at 130 nm and is a central issue at 90 nm.

But H deserves some attention as well, notes Sunil Baliga, Kawasaki LSI's vice president of marketing. Any analog engineer can tell you the behavior of transistors is just as dependent on H as on L. Specifically, as a channel is widened, drive current increases, which translates into greater switching speed for digital circuits. As H is made smaller, the drive current decreases, but so do nearly all the components of leakage current.

This has been of little concern to ASIC users, mainly because ASIC vendors establish the minimum value of H in advance. In this context it is called the grid size. All the transistor channels in a given ASIC family will have widths of some multiple of a fixed H, depending on the drive strength desired. This will be pretty much invisible to an ASIC designer, who sees only cell libraries with timing and leakage models.

Kawasaki's innovation was simple: Offer options on the grid size. Libraries and flows already exist in which individual cells can be selected as faster/high leakage or slower/low leakage in order to minimize leakage current. But why not, on a block-by-block basis, offer a choice of grid sizes as well?

Accordingly, Kawasaki worked with Virage Logic Corp. (www.viragelogic.com) to produce, in addition to its standard eight-grid cell and 12-grid gate array libraries, a set of slower, less leaky seven-grid standard-cell and 10-grid gate array libraries.

This, in effect, gives users a matrix of options: seven, eight, 10 or 12 grids, and low, standard or high threshold voltages. The ASIC designer may select whichever grid size and threshold voltage is appropriate for the block being designed.

The implications are powerful, said Vijay Pathak, Kawasaki's vice president of strategic product development. For example, a system-on-chip can be created using a variety of Kawasaki off-the-shelf intellectual property and memory, with the grid size for each block chosen to meet the maximum performance requirements of the block. Individual use of low-threshold transistors can tune the critical timing nets to give adequate slack.

That means that blocks that can meet their timing goals with seven-grid transistors can be both physically smaller and lower in leakage current than would have been true with an eight-grid block, the only option in conventional ASIC design. Memories can also be tuned, to a lesser degree, by a choice of low- or high-threshold-voltage transistors.

It also means that 10-grid or 12-grid gate array blocks can be freely mixed into a design along with standard-cell blocks. That's important because it means a platform chip can be created with an initial design and then future variants quickly built with just metal-mask changes in the gate array blocks. Or those engineering change orders that never happen can be accommodated without a full mask set re-spin. The cost impact, particularly when a design will have a number of variants, could be huge.

Going with the flows Kawasaki (www.klsi.com) is now working with design automation vendors to make sure that all the advantages of the Matrix ASICs are available in standard flows. Baliga, the marketing vice president, said the company expects to accept customer designs in the second half of this year. Kawasaki LSI engineers are already working on a 90-nm version of the Matrix ASICs.

Baliga summarized the approach as offering benefits in three major areas.

First, it gives users more control over design time and nonrecurring engineering costs on platform-based families of chips by offering blocks of gate array in a cell-based chip.

Second, it provides the flexibility for precise performance-vs.-leakage trade-offs to a degree not even variable-threshold processes could achieve. And third, it gives users the ability to trade performance vs. area for a given netlist-a freedom granted in the past only to those willing to undertake their own library designs.

That's a fair amount of benefit from simply looking twice at the width of a gate.