Xilinx, PMC team on 10-Gbit/s packet-over-Sonet

Xilinx, PMC team on 10-Gbit/s packet-over-Sonet
By Anthony Cataldo, EE Times
March 15, 2001 (1:02 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010313S0106

SAN MATEO, Calif. — Xilinx Inc. has teamed with PMC-Sierra Corp. to introduce a packet-over-Sonet link core for its Virtex II FPGAs, a move the companies believe is needed to support the early adopters of terabit networks.

The soft core conforms to a new interface standard designed for 10-Gbit/second, OC-192 backbones, POS-PHY Level 4. Called PL4 for short, this chip-to-chip interface, which supports both cells and packets, was recently adopted by the Optical Internetworking Forum and the ATM Forum as Utopia 4. Considered the next step beyond the 2.48-Gbit/s OC-48 level, it will play a key role in the development of multiservice switches and gigabit and terabit routers, according to officials at both companies.

To PMC-Sierra, it's important to give users the ability to quickly build in a link layer to match up with forthcoming physical-layer interfaces, which should hit the market next quarter. The standard is still new, and network proces sors are hardly fast enough to handle OC-48, let alone OC-192, said Bill Richardson, director of PMC's partner business group at PMC (Burnaby, British Columbia).

"We're rolling out our own PL4 products, and if nobody can handle the data that comes out of them we'll be sitting and waiting for people to develop their boxes," he said, adding that there will be a "long life" for programmable logic on the data plane.

Your own functionality

Xilinx (San Jose, Calif.), which has made fast, flexible I/O one of the chief selling points of its Virtex II products, is anticipating customers will want to build in their own functionality. That can include tasks done in the data path that are normally handled by the network processor, such as protocol label switching or designating sidebands.

"The features are still evolving, and there are a number of different implementations for multiservice switches or packet-over-Sonet routers," said Ron DiGiuseppe, product marketing manager for the systems in terfaces group at Xilinx. "You can do it in an ASIC, but one of the big values here is time-to-market."

As a chip-to-chip interface, PL4 can be used not only as a connection between the PHY and link layers but also as a connection to the switch fabric and between chips in the data-forwarding plane, Richardson said.

"You may have a chip that does encryption or a traffic manager to augment the network processor," he said. There's also talk of adding a hardware accelerator for encryption or fast lookups, which could also be done in an FPGA, Richardson said.

PMC and Xilinx are teaming up to verify that their devices are compatible at OC-48 and are developing a joint reference design.

The core, which is available now from Xilinx for $18,000, occupies about 40 percent of an XC2V1000 device, which has 1 million system gates and 11,520 logic cells. Though it's a soft core with timing constraints and recommended pinouts, there are no restrictions on where it can be placed on the FPGA, said DiGiuseppe .