eASIC Successfully Qualifies Structured eASIC in 0.13 micron Silicon

The NRE-free Structured eASIC First Family Member Meets the Target Characteristics

Electronica, Munich, Germany, November 9, 2004 -- eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced successful testing and characterization of the first Structured eASIC family member – FA600. The test chips, fabricated by a European IDM partner at 0.13 micron process, were used to test functionality and characterize timing and power for the Structured eASIC device. The FA600 is the smallest member of the company’s Structured eASIC product family. Structured eASIC products feature an innovative combination of FPGA-like flexibility and ASIC-like performance in a unique offering of NRE-free ASIC. The complete product family is scheduled for production release in Q1 2005.

“We are extremely pleased with the success of this most important milestone in the release of the Structured eASIC offering,” said Zvi Or-Bach, eASIC President and CEO. “The Structured eASIC product family is aimed at reviving ASIC design through maskless customization; hence NRE-Free Structured ASIC. eASIC’s unique technology closes the growing NRE gap between ASIC product revenue and ASIC development cost. This paradigm shift has been very well received by the engineering community, and we are grateful to the many engineers who cast their vote to rank eASIC the “#1 Logic & Programmable Logic Ultimate Product” as reported in the EE Times Ultimate Product Survey. Our technology has been validated by world class OEMs and is being used for embedded configurable platforms, and we are now ready to deliver the first NRE-Free Structured ASIC”.

Structured eASIC

eASIC has developed a unique Structured ASIC technology called Structured eASIC. The patented Structured eASIC architecture consists of an array of logic cells (eCells) with SRAM based LUTs (Look Up Tables) and flip-flops. eCells are inter-connected by a segmented wiring grid utilizing upper metal layers, which are customized per customer design with a single Via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom Via-mask for customizing the routing. Moreover, single Via-customization is a perfect fit for Direct-write eBeam lithography. Using Direct-write eBeam completely eliminates the customization tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-Free customized ASIC device.

FA600 – First Structured eASIC Family Member

The FA600 device is the smallest of the four members of the Structured eASIC product family, ranging from 600K to 3M gates, and featuring embedded memory from 0.4M to 1.6M bits, programmable I/Os, PLLs, and embedded microprocessor (8051). Supporting standard CAE tools or tailored Magma design flow, this product family is scheduled for release in Q1 05.

FA600 Specifications:

• Usable ASIC gates: 600K
• bRAM (high density diffused single-port memory blocks): 384 Kb
• bRAM blocks: 12
<>eRAM (configurable distributed dual-port memory, flexibly traded-off with logic gates,  approximately one bit per gate): 640 Kb>
• eRAM blocks: 160
• I/Os: 352
• PLL: 4

Characteristics:

• Gate Speed:
• Fast input to output: 60ps
• Average Gate Delay: 80ps
• Flip-Flop CLK to Q: 100ps
• Operating frequencies: 400 MHz
• Gate Power: 20nW/MHz/gate
• bRAM Power (fully used): 6mW/block @ 100 MHz
• System Power: 350 mW (typical)

Structured eASIC Family Characteristics:

• ASIC gates: 0.6M - 3M
• Memory bits: 0.4M-1.6M
• User I/Os: 352 - 768
• PLL’s: 4-8

About eASIC

eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. eASIC’s technology enables rapid and low-cost ASIC and System-on-Chip designs by its innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express who is viewed by many as the “father of Structured ASIC technology”.
www.eASIC.com

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