InSilicon enhances Java coprocessor core

InSilicon enhances Java coprocessor core
By Nick Flaherty, EE Times UK
February 1, 2001 (11:58 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010131S0069

SANTA CLARA, Calif. — Intellectual-property developer InSilicon Inc. has developed a hardware coprocessor for Java that can run at up to 200 MHz, giving portable systems such as personal digital assistants and smart cards up to 55 times the performance of a Java virtual machine in software.

The JVXextreme core, demonstrated at the DesignCon exhibition and conference, is the second generation of the JVX coprocessor which adds logic pipelining to achieve the speed required for some key capabilities.

InSilicon (San Jose, Calif.) said it has integrated the loop logic from the Java interpreter into the hardware. Instead of using 27 cycles for the loop logic on every byte code, it takes just two, and allows pre-fetching and instruction folding in hardware.

The core also provides up to 64 registers to be used for the Java stack. This compares to four registers in the implementations of Java being added to existing processors, and is a fundamental limit on performance, said Robert Nalesnik, vice president of marketing at InSilicon.

The core, running alongside an ARM9 processor core, scores 6.5 to 9.1 caffeine marks/MHz. This compares with 1.25 to 1.75 caffeine marks/MHz for the previous JVX coprocessor running with an ARM7 at around 30 MHz.

The JVXextreme only has interfaces to ARM7 and ARM9 processors but uses a hardware abstraction layer to port to other architectures without changing the coprocessor.

Power consumption is a function of the number of gates, said Nalesnik, and this has increased from 20,000 to 35,000 gates, increasing the power consumed from 87 microwatts/MHz to 200 microwatts/MHz. Standby power has remained the same at 10 microwatts/MHz.

Nick Flaherty is a contributing editor to Electronics Times, EE Times' sister publication in the United Kingdom.