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Graphcore leverages multiple Mentor technologies for its massive, second-generation AI platform (Tuesday Nov. 10, 2020)
Graphcore has used a range of technologies from Mentor, a Siemens business, to successfully design and verify its latest M2000 platform based on the Graphcore Colossus™ GC200 Intelligence Processing Unit (IPU) processor.
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Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs (Tuesday Nov. 03, 2020)
Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation acceleration flow for Microchip’s Polarfire, SmartFusion2 and RTSX/RTAX FPGA designs using Aldec’s HES-MPF500-M2S150 prototyping board.
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Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts (Thursday Oct. 29, 2020)
Samsung and Cadence collaborate to deliver an integrated flow for designing the next generation of automotive, mobile, data center, artificial intelligence (AI) and other emerging applications
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Mentor's High Density Advanced Packaging solution certified for Samsung Foundry's most advanced packaging process (Thursday Oct. 29, 2020)
Mentor, a Siemens business, today announced that Samsung Foundry has certified Mentor’s digitally integrated High Density Advanced Packaging (HDAP) flow for Samsung’s MDI™ (Multi-Die-Integration) packaging process.
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Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts (Wednesday Oct. 28, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced the release of the 3-nanometer (nm) gate-all-around (GAA) AMS Design Reference Flow, which provides designers a complete front-to-back design methodology for designing analog and mixed-signal circuits using the Synopsys Custom Design Platform.
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Synopsys and Samsung Foundry Collaboration Delivers Optimized Reference Methodology for High-Performance Compute Designs (Wednesday Oct. 28, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with Samsung Foundry to deliver a new certified digital implementation, timing and physical signoff reference flow accelerating high-performance compute (HPC) designs using the Synopsys Fusion Design Platform™.
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Aldec's TySOM Family of Embedded System Development Solutions Now Supports Xilinx PYNQ (Python Productivity for Zynq) (Monday Oct. 26, 2020)
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added PYNQ Python Productivity for Zynq from Xilinx, Inc. to its TySOM family of Xilinx Zynq SoC based boards and its TySOM Embedded Development Kit.
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Synopsys and Samsung Foundry Collaboration Delivers Portfolio of Optimized iPDKs and Methodologies for Advanced Custom Design (Monday Oct. 26, 2020)
Synopsys today announced that in collaboration with Samsung Foundry, more than 30 new interoperable process design kits (iPDKs) have been jointly developed, validated and support the Synopsys Custom Design Platform.
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Arm partners with Mentor to offer complete verification service (Thursday Oct. 22, 2020)
SoC design is a multifaceted process and we are seeing new levels of technological innovation across sectors including automotive, industrial, and healthcare. The complex processor designs that power this technology require more than 100 years of people effort, with a large portion of that time being spent on verification.
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Synopsys 3DIC Compiler Enables Samsung Tapeout of Advanced Multi-die Packaging of High-Bandwidth Memories for HPC Applications (Thursday Oct. 22, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package.
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Breakthrough Synopsys IC Validator Technologies Deliver Faster Physical Signoff Convergence (Tuesday Oct. 20, 2020)
Synopsys today announced the immediate availability of the latest release of its IC Validator physical verification solution, which includes several new innovative technologies to accelerate time-to-results for leading-edge applications.
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Synopsys Accelerates Power Electronics System Design with Virtual Prototyping Solution (Monday Oct. 19, 2020)
Synopsys today announced the industry's most comprehensive virtual prototyping solution to accelerate power electronics system design from concept to validation for power components to large complex systems.
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Perforce Software Accelerates SoC Development With Methodics IPLM 3.0 Launch (Monday Oct. 19, 2020)
Methodics IPLM 3.0 is the next evolution of the Methodics IP lifecycle management platform. Methodics was acquired by Perforce earlier this year.
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Synopsys and SiMa.ai Collaborate to Bring Machine Learning Inference at Scale to the Embedded Edge (Wednesday Oct. 14, 2020)
Synopsys today announced its collaboration with SiMa.ai to bring its machine learning inference at scale to the embedded edge. Through this engagement, SiMa.ai has adopted key products from Synopsys DesignWare® IP, Verification Continuum® Platform, and Fusion Design Platform™ for the development of their MLSoC™
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Synopsys and Samsung Foundry Announce Reference Flow for Predictable Execution of ASIL D-Compliant SoC Design for Automotive Applications (Wednesday Oct. 14, 2020)
Synopsys, Inc. (Nasdaq: SNPS) and Samsung Foundry today announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance.
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TriEye Shortens Time to Market for Next-Generation CMOS-Based SWIR Image Sensors with the Cadence Spectre X Simulator (Wednesday Oct. 14, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that TriEye used the Cadence® Spectre® X Simulator to accelerate the design of a next-generation CMOS-based Short-Wave Infrared (SWIR) image sensor by several months.
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Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform (Tuesday Oct. 13, 2020)
Synopsys today, in a move that expands its industry leadership throughout the design lifecycle, unveiled its Silicon Lifecycle Management (SLM) platform, the industry's first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment.
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New Cadence Clarity 3D Transient Solver Delivers Up to 10X Faster System-Level EMI Simulation (Tuesday Oct. 13, 2020)
System design teams can quickly and accurately simulate large and complex hyperscale, automotive, mobile, and aerospace and defense systems
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Cadence Brings Verification IP to the Chip Level with New System VIP Solution (Tuesday Oct. 13, 2020)
New offering enables up to 10X efficiency gains in system-level testbench assembly, execution and analysis for hyperscale, automotive, mobile and consumer chips
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Synopsys IC Compiler II Delivers First-Pass Silicon Success for Graphcore's Multi-Billion Gate AI Processor (Monday Oct. 12, 2020)
ynopsys, Inc. (Nasdaq: SNPS) today announced that Graphcore achieved first-pass silicon success using the industry-leading IC Compiler™ II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on an industry-leading 7nm advanced process technology.
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Cadence Pegasus Verification System Certified for TSMC N16, N12 and N7 Process Technologies (Monday Oct. 12, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that the Pegasus™ Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies.
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Intento Design Expands Analog Automation with IDX-PVT, Eliminating the Need for Design-by-Verification (Thursday Oct. 08, 2020)
With the number of corners often reaching thousands, intuitively added “design margin” doesn’t work anymore. Designers spend time in endless loops, just to reach one well centered design with enough margin to cover the performance and satisfy the PVT variation.
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SmartDV Unveils SmartConf Testbench Generator (Wednesday Oct. 07, 2020)
martDV™ Technologies, the Proven and Trusted choice for Design and Verification intellectual property (IP), today unveiled SmartConf testbench generator, an add-on automation tool to its extensive Verification IP portfolio.
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Efabless Extends Partnerships for Rapid Development Solution of Custom ICs (Monday Oct. 05, 2020)
Efabless announced today a collaboration with imec, a world-leading research and innovation hub in nanoelectronics and digital technologies to support customers with low-cost rapid solutions for IC development.
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Toshiba Information Systems Adopts Blue Pearl Software Visual Verification Suite by to Improve Quality and Accelerate FPGA and ASIC Development (Monday Oct. 05, 2020)
Blue Pearl Software Inc.,today announces that Japan’s Toshiba Information Systems, a leading company in information services, has adopted the Blue Pearl Visual Verification™ Suite to improve the productivity and quality of their FPGA and ASIC development.
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GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design (Monday Sep. 28, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a collaboration with GLOBALFOUNDRIES® (GF®) that resulted in the availability of a Mixed-Signal OpenAccess process design kit (PDK) that supports GF’s 22FDX® platform.
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GLOBALFOUNDRIES and Mentor Collaborate to Launch New Semiconductor Verification Solution Embedded with Advanced Machine Learning Capabilities (Monday Sep. 28, 2020)
New industry-leading ML-enhanced DFM solution for designing on GF 12LP+ platform can provide customers with a more efficient experience and contribute to a faster time to market
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Efabless Expands support for Cloud-based Design Platform (Friday Sep. 25, 2020)
The new offering, which includes digital design and low cost ASIC development based on configurable design templates, provides a full “semiconductor ecosystem in a box” that brings the power of GF’s 130G solution to a network of previously unserved OEMs, IC designers and IP providers. New capabilities are available on GF’s 130nm platform now.
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Synopsys and GLOBALFOUNDRIES Collaborate to Expand Fusion Compiler Benefits for Latest Platforms (Thursday Sep. 24, 2020)
Synopsys today announced its latest collaboration with GLOBALFOUNDRIES (GF®) to drive productivity and power, performance, and area (PPA) enhancements for mutual customers deploying the Synopsys Fusion Compiler™ RTL-to GDSII product – the industry's only single data model and golden-signoff enabled implementation solution.
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NSITEXE Successfully Develops Multiple Custom Processors for Automotive Applications in Half the Time with Synopsys ASIP Designer Tool (Thursday Sep. 17, 2020)
Synopsys today announced that NSITEXE, a group company of DENSO Corporation that develops and sells high-performance semiconductor IP, used the Synopsys ASIP Designer Tool in the development of five specialized custom processors, including dedicated vector-processing engines, for its automotive data flow processor (DFP) platform.