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Technology Analyzer transforms analog IP reuse (Monday Sep. 14, 2020)
Thalia Design Automation, experts in targeted automation for analog and mixed signal design and IP reuse, today announced the launch of its Technology Analyzer, a further enhancement of its AMALIA IP reuse platform.
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Synopsys Introduces the Industry's First Unified Electronic and Photonic Design Platform (Wednesday Sep. 09, 2020)
OptoCompiler is the industry's first unified electronic and photonic design platform, combining mature and dedicated photonic technology with Synopsys' industry-proven electronic design tools and methods to enable engineers to produce and verify complex PIC designs quickly and accurately.
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Thalia and Dolphin Design announce partnership to transform analog IP re-use economics and to accelerate time to market (Monday Sep. 07, 2020)
Thalia Design Automation, experts in targeted automation for analog and mixed signal design and IP reuse, and Dolphin Design, a leading company in semiconductor IPs and platform solutions, today announced a partnership transforming the way IP portfolios are expanded and managed, delivering new IPs to market faster and more cost-effectively than through conventional processes.
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Mentor achieves certifications for TSMC's leading-edge 3nm process technology (Thursday Sep. 03, 2020)
Mentor, a Siemens business, today announced that TSMC has certified multiple Mentor product lines and tools for the foundry’s recently announced 3nm (N3) process technology.
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Mentor's Questa and Veloce platforms help SimpleMachines dramatically speed development of its first AI processor (Thursday Aug. 27, 2020)
Mentor, a Siemens business, today announced that artificial intelligence (AI) silicon startup SimpleMachines (SMI) successfully developed its first-generation product using Mentor’s Enterprise Verification Platform including the Questa® simulation platform and Veloce® Strato emulation hardware, as well as Mentor Consulting’s cloud-based Emulation-as-a-Service (EaaS) offering.
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Cadence IC Packaging Reference Flow Certified for the Latest TSMC Advanced Packaging Solutions (Wednesday Aug. 26, 2020)
Cadence today announced the certification of the Cadence® tools in TSMC reference flows for TSMC’s latest InFO and CoWoS® advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS®-S)
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Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows (Tuesday Aug. 25, 2020)
Synopsys today announced that Synopsys and TSMC have collaborated to deliver certified design flows for advanced packaging solutions using the Synopsys 3DIC Compiler product for both silicon interposer based Chip-on-Wafer-on-Substrate (CoWoS®-S) and high-density wafer-level RDL-based Integrated Fan-Out (InFO-R) designs.
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Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design (Tuesday Aug. 25, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified Synopsys' digital and custom design platforms for TSMC's 3-nanometer (nm) process technology.
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Synopsys IC Validator, Running on AMD EPYC Processor Powered Azure Virtual Machines, Verifies AMD Radeon Pro VII GPU Design in Under Nine Hours (Thursday Aug. 20, 2020)
Synopsys today announced that its IC Validator physical verification solution running on Microsoft Azure completed a verification run of the AMD Radeon™ Pro VII GPU, which includes more than 13 billion transistors, in less than nine hours.
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Clue Technologies adopts OneSpin's verification solution for avionic computing systems (Thursday Aug. 20, 2020)
Clue Technologies has announced that it has adopted OneSpin’s advanced coverage-driven assertion-based verification solution, allowing it sell its safety-certified intelligent computing systems to aircraft manufacturers.
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S2C and Mirabilis Design Teamup to Deliver a Heterogeneous Solution for SoC Architecture Exploration and Verification (Tuesday Aug. 18, 2020)
S2C and Mirabilis Design today announced the collaboration and delivery of a hybrid SoC architecture exploration solution that reuses available RTL-based blocks to accelerate model construction and speed-up very complex simulations.
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Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform (Tuesday Aug. 18, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Nuvoton has deployed the Cadence® Palladium® Z1 Enterprise Emulation Platform to accelerate the development of its microcontroller units (MCUs) for industrial and consumer applications.
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Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions (Thursday Aug. 13, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence® XceliumTM Logic Simulator has been enhanced with machine learning technology (ML), called Xcelium ML, to increase verification throughput.
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Synopsys Introduces Integrated Electric Vehicle Virtual Prototyping Solution (Wednesday Aug. 12, 2020)
The integrated solution leverages Synopsys' best-in-class virtual prototyping technologies, including Virtualizer™, Silver, TestWeaver® and SaberRD, enhanced for the specific needs of electric vehicle system development.
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Mentor extends industry-leading EDA software support for Samsung Foundry's 5/4nm process technologies (Monday Aug. 10, 2020)
Mentor, a Siemens business, today announced that its industry-leading Calibre™ nmPlatform and Analog FastSPICE (AFS) custom and analog/mixed-signal (AMS) circuit verification platform are now qualified for Samsung Foundry’s newest process technologies.
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Intento Design announces the launch of ID-Calibre, an ID-Substrate extension for behavioural TCAD simulation on a complete AMS chip (Thursday Jul. 30, 2020)
After the launch of ID-Substrate, a reliability tool for early detection and prevention of all substrate parasitics, Intento Design presents ID-Calibre, an AI-based calibration tool (full release before the end of 2020)
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Cadence and UMC Certify mmWave Reference Flow on 28HPC+ Process for Advanced RF Designs (Thursday Jul. 23, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) and United Microelectronics Corporation (UMC), a global semiconductor foundry, today announced that the Cadence® millimeter wave (mmWave) reference flow has achieved certification for UMC’s 28HPC+ process technology.
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European Space Agency, Blue Pearl Software and ADIUVO Engineering Partner Contract to Improve the usability of ESA Soft-Cores (Thursday Jul. 23, 2020)
Blue Pearl Software today announced a contract with European Space Agency (ESA) and ADIUVO Engineering aimed at improving the usability of the ESA soft-core IP.
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Aldec Provides Static Verification for RISC-V Designs with the latest release of ALINT-PRO (Thursday Jul. 23, 2020)
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added a RISC-V focused static verification rule set to ALINT-PRO™; rules that statically validate HDL code quality prior to simulation.
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Flex Logix Announces EFLX eFPGA And nnMAX AI Inference IP Model Support For The Veloce Strato Emulation Platform From Mentor (Tuesday Jul. 21, 2020)
Flex Logix® Technologies today announced support for EFLX eFPGA IP and nnMAX™ AI Inference IP emulation models for use on Mentor's Veloce® Strato™ emulation platform.
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New Analog FastSPICE eXTreme technology boosts verification performance by up to 10X (Tuesday Jul. 21, 2020)
Mentor, a Siemens business, today announced significant advances in the Analog FastSPICE Platform with the introduction of Analog FastSPICE eXTreme technology for nanometer-scale verification of large, post-layout analog designs.
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Synopsys VCS Used by Graphcore to Verify Next-Generation Colossus GC200 IPU (Monday Jul. 20, 2020)
Synopsys today announced that Graphcore used the Synopsys VCS® simulation solution with Verdi® debug to verify its recently announced game-changing Colossus™ GC200 Intelligence Processing Unit (IPU).
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SmartDV, Aldec Partner to Link SmartDV's Verification IP with Aldec's Riviera-PRO Simulator (Monday Jul. 20, 2020)
SmartDV™ Technologies and Aldec today inked an agreement linking SmartDV’s Verification IP with Aldec’s Riviera-PRO™ high-performance simulation and debugging tool.
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Mentor introduces Calibre nmLVS-Recon technology to dramatically streamline overall IC circuit verification (Monday Jul. 20, 2020)
To help integrated circuit (IC) designers achieve design closure faster, Mentor, a Siemens business, today announced the extension of their powerful Calibre® Recon technology to the Calibre nmLVS circuit verification platform.
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Axiomise Announces the Release of the Next-Generation RISC-V App (Thursday Jul. 16, 2020)
Axiomise® announced the availability of its new RISC-V formal verification app formalISA®. The app supports all the leading commercial formal verification tools and includes a new coverage solution for formal verification of RISC-V processors.
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Flex Logix Announces EFLX eFPGA Emulation Models For The Cadence Palladium Z1 Platform (Monday Jul. 13, 2020)
Flex Logix® Technologies, Inc., a leading supplier of embedded FPGA (eFPGA) and AI Inference IP, architecture and software, today announced the availability of EFLX® eFPGA IP emulation models for use on the Cadence Palladium® Z1 Enterprise Emulation Platform, the industry's first data center-class emulation system.
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Mentor collaborates with Samsung Foundry to boost product yield and streamline in-fab memory testing (Monday Jul. 13, 2020)
Mentor today announced it has collaborated with Samsung Foundry to develop a new reference kit designed to help mutual customers substantially simplify and streamline the testing, diagnosis and repair of embedded memory in advanced systems-on-chip (SoCs) during fabrication.
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Aldec Adds Customizable Tool Qualification Data Package to ALINT-PRO for DO-254 Projects (Thursday Jul. 02, 2020)
Aldec has added a customizable tool qualification data package to ALINT-PRO™ to save users considerable time when qualifying the tool’s use in projects requiring Design Assurance Levels (DAL) A and B under DO-254 guidance.
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Sigasi Introduces Software Development Kit for Electronic Design Automation Tools (Thursday Jul. 02, 2020)
Sigasi, a leading developer of HDL design solutions, today announced Sigasi’s Software Development Kit (SDK) for developers of third party electronic design automation (EDA) tools.
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Synopsys and Arm Extend Strategic Partnership to Deliver Superior Full-Flow Quality-of-Results and Time-to-Results (Monday Jun. 29, 2020)
Synopsys today announced it has signed a multi-year agreement with Arm for the purpose of accelerating design and verification of Arm®-based system-on-chips (SoCs) for mutual customers.