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ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
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Synopsys Broadens Collaboration with EPFL (Friday Jun. 26, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced it has broadened its ongoing academic collaboration by entering into an agreement to license novel digital synthesis technologies from EPFL, the Swiss Federal Institute of Technology in Lausanne, Switzerland.
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Synopsys Collaboration with Samsung Foundry Enables Rollout of Samsung SAFE Cloud Design Platform (Thursday Jun. 18, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced it has collaborated with Samsung Foundry, as an early leading partner, in Samsung's delivery of its SAFE Cloud Design Platform, designed as a ready-to-use cloud platform for Samsung Foundry customers and ecosystem partners.
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Cadence Collaborates with TSMC and Microsoft to Reduce Semiconductor Design Timing Signoff Schedules with the Cloud (Tuesday Jun. 16, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the results of a three-way collaboration with TSMC and Microsoft focused on utilizing cloud infrastructure to reduce semiconductor design signoff schedules.
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Synopsys, TSMC and Microsoft Azure Deliver Highly Scalable Timing Signoff Flow in the Cloud (Monday Jun. 15, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with TSMC and Microsoft has delivered a ground-breaking, highly scalable timing signoff flow for use in the cloud. This extensive, multi-month collaboration among the three industry partners speeds up the path to signoff next-generation systems-on-chips (SoCs).
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Truechip Announces Shipping of Performance Analyzer Tool Kit to Aaroh Labs (Thursday Jun. 11, 2020)
Truechip, the Verification IP Specialist, today announced that it has shipped the commercial version of performance analyzer kit to its customer Aaroh Labs.
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Real Intent Announces Verix Multimode DFT Static Sign-Off Tool (Thursday Jun. 11, 2020)
Real Intent, Inc., today announced Verix DFT, a full-chip, multimode DFT static sign-off tool. Verix DFT’s comprehensive set of fine-grained DFT rules help designers to rapidly identify design violations and improve scan testability and coverage.
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Efinix Completes Trion FPGA Family for Edge Computing, AI/ML and Vision Processing Applications Using Cadence Digital Full Flow Solution (Thursday Jun. 11, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Efinix successfully utilized the Cadence® digital full flow solution to complete the first wave of its Trion family of field programmable gate arrays (FPGAs), which are used in edge compute, AI/ML and vision processing applications for the mobile, industrial and surveillance markets.
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Synopsys Delivers the Industry's Only Complete Workflow for Automotive Lighting Design and Visualization in CATIA (Wednesday Jun. 10, 2020)
Synopsys today announced the latest release of its LucidShape® CAA V5 Based software product to provide the industry's only complete design and visualization workflow solution for automotive lighting design within the CATIA V5 environment.
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Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies (Wednesday Jun. 03, 2020)
Cadence today announced that its digital full flow and custom/analog tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies.
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Ambarella Adopts Cadence Clarity 3D Solver for AI Vision Processor Development (Monday Jun. 01, 2020)
Cadence today announced that Ambarella, Inc. has adopted the Cadence® Clarity™ 3D Solver for design of their next-generation AI vision processors.
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Samsung Foundry Certifies Synopsys Design Compiler NXT for 5/4nm FinFET Process Technologies (Monday Jun. 01, 2020)
Synopsys today announced that the Synopsys Design Compiler® NXT synthesis solution has been qualified by Samsung Foundry for its 5/4-nanometer FinFET process technologies.
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GOWIN Semiconductor Integrates their latest HDMI/DVI RX and TX IP into GOWIN EDA IP Generator (Wednesday May. 27, 2020)
GOWIN Semiconductor Corp., the world’s fastest-growing programmable logic company, announces the release of their HDMI/DVI RX and TX IPs in GOWIN EDA’s IP Generator providing low cost video interfacing and connectivity solutions for various embedded applications.
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Cadence to Optimize Digital Full Flow and Verification Suite for Arm Cortex-A78 and Cortex-X1 CPU Mobile Device Development (Wednesday May. 27, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has broadened its long-standing collaboration with Arm to advance the development of mobile devices based on the Arm® Cortex®-A78 and Cortex-X1 CPUs.
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Synopsys Enables Tapeout Success for Early Adopters of Arm's Next Generation of Mobile IP (Tuesday May. 26, 2020)
A range of Synopsys solutions, including the Synopsys Fusion Design Platform™, Verification Continuum™ Platform, and DesignWare® Interface IP, were used in the design of smartphones, laptops, other mobile devices, 5G, augmented reality, and machine learning products based on Arm's new processors.
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Panasonic Adopts Synopsys Custom Design Platform to Accelerate Next-Generation Automotive and Industrial Products (Friday May. 22, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Panasonic Corporation has selected the Synopsys Custom Design Platform for its total design flow to develop next generation analog and mixed-signal products after the completion of a rigorous technical evaluation and successful migration of legacy design flows and data.
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Mirabilis Design creates the first RISC-V system-level architecture exploration solution (Wednesday May. 20, 2020)
Mirabilis Design announced today the VisualSim RISC-V system modeling and simulation environment. With this release, VisualSim provides a complete RISC-V modeling package for developers of RISC-V IP, designers of RISC-V processors and systems engineers developing applications using RISC-V components.
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Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput (Tuesday May. 19, 2020)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the new release of the Cadence® digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).
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Synopsys and TSMC Collaborate to Enable Designs of HPC, Mobile, 5G, and AI SoCs with Certified Solutions on TSMC N5 and N6 Processes (Monday May. 18, 2020)
Strategic collaboration with TSMC delivers additional gains in performance and ultra-low power, and accelerates the path to next-generation designs
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Mentor's Calibre and Analog FastSPICE platforms achieve certification for TSMC's newest processes (Monday May. 18, 2020)
Mentor, a Siemens business, today announced that it has achieved certification for a broad array of Mentor integrated circuit (IC) design tools for TSMC’s industry-leading N5 and N6 process technologies.
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Synopsys Introduces 3DIC Compiler, Industry's First Unified Platform to Accelerate Multi-die System Design and Integration (Tuesday Apr. 28, 2020)
Unique platform delivers automation and visualization for 2.5D/3D package design and implementation, with power, thermal, and noise-aware optimization
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Imperas Leading RISC-V CPU Reference Model for Hardware Design Verification Selected by Mellanox (Tuesday Apr. 21, 2020)
Imperas Software today announced that Mellanox Technologies, a leading supplier of high-performance, end-to-end smart interconnect solutions for datacenter servers and storage systems, has selected the Imperas advanced hardware verification of RISC-V processors.
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GLOBALFOUNDRIES Qualifies Synopsys' IC Validator for Signoff Verification on 22FDX Platform (Thursday Apr. 16, 2020)
Synopsys today announced that GLOBALFOUNDRIES® (GF®) has qualified Synopsys' IC Validator for its 22FDX® platform. With IC Validator physical verification, customers striving to take advantage of the low-power and performance benefits of GF's 22-nanometer FD-SOI technology can now quickly verify that their designs meet signoff requirements for manufacturability compliance and maximum yield.
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Groq Adopts Synopsys ZeBu Server 4 to Develop Breakthrough AI Chip (Monday Apr. 13, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Groq has adopted the Synopsys ZeBu® Server 4 emulation solution for its Tensor Streaming Processor (TSP) architecture development. ZeBu Server 4 performance and capacity enabled first silicon success of Groq's TSP architecture for artificial intelligence (AI) and machine learning platforms.
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Faraday Adopts Synopsys' Platform Architect and Hybrid Prototyping Solutions to Expand Design Services (Monday Apr. 06, 2020)
Synopsys today announced that Faraday Technology Corporation has expanded their SoC design services to use Synopsys prototyping solutions, including Platform Architect™ for SoC architecture design and optimization, and HAPS® FPGA-based prototyping for hardware and software co-design to accelerate time-to-market.
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Synopsys Expands Collaboration with Broadcom for 7nm and 5nm Designs (Thursday Apr. 02, 2020)
Synopsys today announced its expanded collaboration with Broadcom Inc. for the creation of semiconductor solutions using Synopsys' Fusion Design Platform™ to address a host of design challenges at 7nm and beyond.
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Compact Model Developed at CEA-Leti for FD-SOI Technologies Designated as a Chip-Industry Standard (Thursday Apr. 02, 2020)
L-UTSOI, a “compact model” dedicated to FD-SOI technologies and developed by CEA-Leti, has been selected as a standard model by the Compact Model Coalition (CMC), a working group composed of the major semiconductor companies and part of the Silicon Integration Initiative (Si2).
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SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design (Wednesday Mar. 25, 2020)
Synopsys, Inc. today announced that SiFive, Inc. has selected Synopsys Fusion Design Platform™ and Verification Continuum® platform to enable rapid cloud-based design of next-generation customer silicon products.
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InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL (Tuesday Mar. 24, 2020)
Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has successfully completed the verification of its soft IP portfolio for the latest Lattice Semiconductor® CrossLink™ FPGA family, using Active-HDL™ for mixed-HDL simulation and debugging.
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Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput (Tuesday Mar. 17, 2020)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the new release of the Cadence® digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).
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Synopsys Unveils RTL Architect To Accelerate Design Closure (Monday Mar. 16, 2020)
Synopsys today announced the immediate availability of RTL Architect™, an innovative product that signifies a shift-left for RTL design closure. Synopsys RTL Architect is the industry's first physically aware RTL design system, which reduces the SoC implementation cycle in half and delivers superior quality-of-results (QoR).