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ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
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DAeRT: eInfochips' DFT Framework that Increases Productivity and Reduces Silicon Development Cycle (Monday Mar. 16, 2020)
eInfochips launches DAeRT (DFT Automated Execution and Reporting Tool) - an automated framework for the semiconductor industry, which provides a complete solution for DFT, starting from architecture to implementation for any ASIC (Application Specific Integrated Circuit).
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Synopsys Advances State-of-the-Art in Electronic Design with Revolutionary Artificial Intelligence Technology (Wednesday Mar. 11, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced a major breakthrough in electronic design technology with the introduction of DSO.ai™ (Design Space Optimization AI), the industry's first autonomous artificial intelligence application for chip design.
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Synopsys Custom Design Platform Secures Full-flow Displacement of Legacy Design Tools at Alphawave (Tuesday Mar. 10, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that silicon IP provider Alphawave has adopted the Synopsys Custom Design Platform to accelerate the design of multi-standard connectivity solutions.
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UMC certifies Mentor product lines for its new 22nm ultra-low-power process technology (Thursday Mar. 05, 2020)
Mentor, a Siemens business, today announced that multiple Mentor product lines are now certified for United Microelectronic Corporation’s (UMC’s) 22uLP (ultra Low Power) process technology, including Mentor’s Calibre™ platform, Analog FastSPICE™ platform, and Nitro-SoC digital design platform.
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Samsung Adopts Synopsys' Machine Learning-Driven IC Compiler II for its Next-Generation 5nm Mobile SoC Design (Thursday Mar. 05, 2020)
Synopsys today announced that Samsung has adopted the industry-leading IC Compiler™ II place-and-route solution, part of the Synopsys Fusion Design Platform™, for its next-generation 5nm mobile system-on-chip (SoC) production design.
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Defacto Announces STAR 8.0 and Provides a Unified "All-in-One" SoC Design Solution to Help Conciliating Between RTL, IP-XACT, UPF, SDC, and Physical Design Information (Wednesday Mar. 04, 2020)
Defacto’s latest Release STAR 8.0 helps to lower the complexity of typical SoC Integration design flows where several sources of design information are required to start building an SoC, including design descriptions (mixed RTL code, gate-level netlist, physical) and design collaterals (power intent, timing constraints).
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Synopsys Announces Next-Generation VC SpyGlass RTL Static Signoff Platform (Thursday Feb. 27, 2020)
Synopsys, Inc. (Nasdaq: SNPS), today announced general availability of the VC SpyGlass™ RTL Static Signoff platform, part of the Synopsys Verification Continuum™ platform, which builds on the proven SpyGlass® technology.
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Imperas Collaborates with Mentor on RISC-V Core RTL Coverage Driven Design Verification Analysis (Monday Feb. 24, 2020)
Imperas Software today announced a collaboration with Mentor, a Siemens business, on the latest hardware Design Verification (DV) Flow for RISC-V processor implementations, to ensure an easy to use reference methodology is available to processor developers, users and adopters across the RISC-V ecosystem.
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Gowin Semiconductor Adds Ubuntu Support to their Gowin EDA FPGA Software for Improved Artificial Intelligence and IoT Development Toolchain Integration (Thursday Feb. 20, 2020)
GOWIN Semiconductor Corp., the world’s fastest-growing programmable logic company, announces support for their GOWIN EDA FPGA development software in Ubuntu Operating System enabling developers with a single environment for Artificial Intelligence and IoT connectivity development.
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Weebit Nano and Silvaco Develop New Simulation Capabilities to Increase ReRAM Adoption (Thursday Feb. 20, 2020)
Weebit Nano Ltd and Silvaco, Inc. today announced that they have successfully modeled the electrical behavior of Weebit’s silicon oxide (SiOx) Resistive Random Access Memory (ReRAM) device
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Synopsys' Fusion Compiler Adopted by AMD (Wednesday Feb. 19, 2020)
Synopsys, Inc. (Nasdaq: SNPS) today announced that AMD is deploying Synopsys' Fusion Compiler™ RTL-to-GDSII product for its full-flow, digital-design implementation. Based on an evaluation process, the Fusion Compiler product delivered industry-leading performance, power and area (PPA) metrics.
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UltraSoC collaborates with PDF Solutions to prevent in-life product failures using end-to-end analytics and advanced machine learning techniques (Thursday Feb. 13, 2020)
UltraSoC today announced a collaboration with PDF Solutions® [NASDAQ: PDFS] that combines comprehensive data analytics with advanced machine learning (ML) techniques, with the goal of predicting and preventing chip failures in the field with unprecedented accuracy.
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Mythic adopts Mentor's Analog FastSPICE and Symphony platforms for AI processor design (Wednesday Feb. 12, 2020)
Mentor, a Siemens business, today announced that Mythic, an artificial intelligence (AI) processor company, has standardized on Mentor’s Analog FastSPICE™ Platform for custom circuit verification and device noise analysis.
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Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation (Tuesday Jan. 28, 2020)
Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that Cobham Gaisler has successfully verified its first RISC-V line of processors, called NOEL-V™, using Riviera-PRO™ for mixed-HDL simulation.
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Cadence Expands Collaboration with Broadcom for 5nm and 7nm Designs (Tuesday Jan. 14, 2020)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it expanded its collaboration with Broadcom Inc. for the creation of semiconductor solutions targeting next-generation networking, broadband, enterprise storage, wireless and industrial applications.
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Bluespec, Inc. to Open Source Its Proven BSV High-level HDL Tools (Tuesday Jan. 07, 2020)
Bluespec, Inc. will open source its BSV development tools on January 31, 2020. The company is contributing this powerful field-proven technology to the open source hardware community to reinforce an industry uptick in the use of high-level HDLs that will address challenging new design and verification problems.
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zGlue Launches ChipBuilder Pro to Quickly and Easily Enable the Next Generation of Consumer Experiences on IoT and AI-Powered Devices (Monday Jan. 06, 2020)
zGlue, an as-a-service company for creating AI and IoT-powered chips on-demand, today announced its ChipBuilder Pro Package to quickly and easily enable the next generation consumer experiences on IoT and AI-powered devices.
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NEC Selects Synopsys ZeBu Server 4 Emulation Solution for Super Computer Verification (Friday Dec. 20, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that NEC, a key player in high-performance computing (HPC), has selected Synopsys' ZeBu® Server 4 as its emulation solution for the verification of its SX-Aurora TSUBASA high-performance compute solution products.
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SLX FPGA v2019.4 Delivers an Average of 45x HLS Performance Improvement (Wednesday Dec. 18, 2019)
Silexica has announced the release of SLX FPGA v19.4. Designed to help developers prepare and optimize C/C++ code for high-level synthesis (HLS) in Xilinx’s Vivado and Vitis HLS design flows.
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Aldec Enhances Riviera-PRO's VHDL and UVVM Support (Wednesday Dec. 18, 2019)
Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).
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Mentor collaborates with Arm on unique eMRAM test solution using Samsung FDSOI technology (Monday Dec. 16, 2019)
Mentor today announced it will provide a unique IC test solution for the eMRAM (embedded Magnetoresistive Random Access Memory) compiler IP from Arm, built on Samsung Foundry’s 28nm FDSOI process technology.
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Enflame leverages Mentor's Tessent DFT solutions for innovative cloud AI chip targeting neural network training (Monday Dec. 16, 2019)
Mentor, a Siemens business, today announced that leading artificial intelligence (AI) solution provider Enflame Technology recently used Mentor’s Tessent™ software product family to successfully meet silicon test requirements and achieve rapid test bring-up for its new Deep Thinking Unit (DTU) chip.
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Breker Verification Systems Launches Unique RISC-V TrekApp for Automated, High-Coverage System Integration Test Suite Synthesis (Friday Dec. 13, 2019)
Breker Verification Systems, the leading provider of Test Suite Synthesis tools based on the Portable Stimulus Standard (PSS), today introduced its RISC-V TrekApp, a complete, automated test content generator for RISC-V system integration testing.
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Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications (Tuesday Dec. 10, 2019)
Cadence Innovus Implementation System and Voltus IC Power Integrity Solution enable GUC to achieve first-pass silicon success and meet GHz performance target for multi-billion gate designs
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Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM (Wednesday Dec. 04, 2019)
Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification capabilities of Active-HDL™, the company’s popular Windows-based Integrated Development Environment (IDE) for FPGA design creation and simulation.
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Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation (Tuesday Dec. 03, 2019)
National Instruments Corporation (Nasdaq: NATI) and Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a system innovation strategic alliance to create an integrated design to test flow,
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Graphcore leveraged Mentor's Questa technologies to verify massive Colossus GC2 AI processor (Tuesday Nov. 19, 2019)
Mentor, a Siemens business, has revealed that artificial intelligence (AI) processing leader Graphcore leveraged Mentor’s Questa™ software for simulation and verification of IP technologies to rapidly verify Graphcore’s massive Colossus GC2 Intelligence Processing Unit (IPU).
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Synopsys Custom Compiler Adopted by Samsung Foundry to Accelerate IP Design for 5LPE Process Technology with EUV Technology (Monday Nov. 18, 2019)
Synopsys today announced that Samsung Electronics has adopted the Synopsys Custom Design Platform, based on the Custom Compiler™ design environment, to design IP for its 5-nanometer (nm) Low-Power Early (LPE) process with Extreme Ultraviolet (EUV) lithography technology.
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Mirabilis Design unveils the first rapid prototyping platform for Artificial Intelligence Processors and Applications (Thursday Nov. 14, 2019)
Mirabilis Design announced the immediate release of VisualSim AI Evaluator for quick architecture exploration of Artificial Intelligence (AI) and Machine Learning. This AI evaluator combines analog, digital, power and network modeling to select the right architecture for the accelerator and the right configuration of accelerators and memories for a target application.
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Mentor introduces Tessent Safety ecosystem to meet IC test requirements of the autonomous vehicles era (Tuesday Nov. 12, 2019)
Mentor, a Siemens business, today introduced the new Tessent™ software Safety ecosystem – a comprehensive portfolio of best-in-class automotive IC test solutions from Mentor with links to its industry-leading partners. The program helps IC design teams meet the increasingly stringent functional safety requirements of the global automotive industry.