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NVIDIA Deploys the New Cadence Protium X1 Platform to Accelerate Software Development of Large-Capacity GPUs (Tuesday May. 28, 2019)
Cadence today announced that NVIDIA Corporation has deployed the Cadence® Protium™ X1 FPGA-Based Platform for early software development to accelerate the development of its large-capacity GPUs for gaming, artificial intelligence (AI), automotive and other market segments.
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Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development (Tuesday May. 28, 2019)
Cadence today expanded its Verification Suite and System Innovation offerings with the announcement of the Cadence® Protium™ X1 Enterprise Prototyping Platform, the first data center-optimized FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
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Synopsys Introduces PrimeYield for 100X Faster SoC Yield Analysis and Optimization (Tuesday May. 28, 2019)
Synopsys today announced the availability of its PrimeYield™ solution, a breakthrough for pre-silicon design yield analysis enabled by patented fast statistical methods and accelerated with advanced machine learning technology.
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IC Compiler II with Advanced Fusion Technologies Delivers Optimal QoR and Reduces ECO Turnaround Time More Than 40% at Juniper Networks (Tuesday May. 28, 2019)
Synopsys today announced that its innovative IC Compiler™ II place-and-route solution with Advanced Fusion technologies has been deployed at Juniper Networks, where it delivered better power and area results.
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Silvaco Announces Viola I0-X - 10X Faster I/O Pad Characterization for Nanometer Silicon (Tuesday May. 28, 2019)
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Synopsys and Arm Collaborate to Enable Tapeouts by Early Adopters of Arm's Latest Premium Mobile Processors (Monday May. 27, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys and Arm have collaborated to enable tapeouts of optimized system-on-chip (SoC) design and verification for early adopters of Arm's latest premium mobile processor IP, including the Arm® Cortex®-A77 CPU and Mali™-G77 GPU.
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Cadence Full-Flow Digital and Signoff Tools Optimized for New 7nm Arm Cortex-A77 CPU (Monday May. 27, 2019)
Cadence today announced that its full-flow digital and signoff tools support the new high-performance, high-efficiency Arm® Cortex®-A77 CPU for next-generation smartphones, laptops, and other mobile devices.
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TSMC-Certified OIP Virtual Design Environment with Synopsys Tools Now Available on Google Cloud (Thursday May. 23, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC's Open Innovation Platform® Virtual Design Environment (OIP VDE) with Synopsys tools is now certified and available on the Google Cloud Platform (GCP).
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Synopsys Delivers 100X Faster Formal Verification Closure for AI, Graphics, and Processor Designs (Thursday May. 23, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today introduced the Datapath Validation (DPV) app as part of its VC Formal® solution. The DPV app leverages proven HECTOR™ technology to deliver exhaustive formal verification closure on datapath-intensive designs during the design and verification cycle for broad market adoption.
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OneSpin's Newest App Assures Quality of RISC-V Processor Cores for Safety-, Security-Critical Applications (Thursday May. 23, 2019)
OneSpin® Solutions today unveiled the formal OneSpin 360 DV RISC-V Verification™ App, the first App in the OneSpin 360 DV RISC-V Integrity™ Verification Solution for safety- and security-critical applications.
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Thinci Deploys Full Cadence Verification Suite for AI Designs, Accelerating Project Schedule by Months (Thursday May. 23, 2019)
Cadence Design Systems today announced that Thinci has deployed the full Cadence® Verification Suite to accelerate the design and verification of its machine learning and artificial intelligence (AI) system-on-chip (SoC) designs.
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Synopsys Announces Software-driven SoC Power Analysis Solution, Enabling 1000X Faster Time-to-Results (Thursday May. 23, 2019)
New ZeBu Power Analyzer Enables Emulation-based Power Analysis for Billion-cycle Software Workloads Not Feasible with Traditional Methods
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ClioSoft and Silvaco Collaborate to Integrate ClioSoft's SOS Design Data Management Platform with Silvaco's Analog Custom Design Tools (Tuesday May. 21, 2019)
ClioSoft and Silvaco today announced SOS for Silvaco, a SoC design management platform developed by ClioSoft, Inc. in collaboration with Silvaco, Inc.
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Cadence Palladium and Protium Platforms Enable Innovium to Accelerate First-Pass Silicon Success for the Data Center Market (Monday May. 20, 2019)
Cadence today announced that Innovium has adopted the Palladium® Z1 Enterprise Emulation Platform and the Protium™ S1 FPGA-Based Prototyping Platform to achieve first-pass silicon success on its high-performance, scalable, production-ready TERALYNX™ ethernet switch for the data center.
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SmartDV Reduces Protocol Debug Time with Smart ViPDebug (Thursday May. 16, 2019)
SmartDV™ Technologies today unveiled Smart ViPDebug™, a protocol debugger that reduces debug time by rapidly identifying violations and reducing the time needed to find the cause of violations through its linked waveform and transaction database views.
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Silicon Labs Partners with Pulsic, Selecting Animate as Its Automated Layout Solution for Analog IC Designs (Wednesday May. 15, 2019)
Pulsic, the premier provider of custom physical design tools for precision design automation of analog/mixed-signal designs, today announced that Silicon Labs will use Pulsic’s Animate solution for its forthcoming IC analog designs.
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Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores (Tuesday May. 14, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys and Arm have expanded their collaboration to deliver QuickStart Implementation Kits (QIKs) supporting Synopsys' Fusion Compiler™ solution, the industry's only fully-integrated RTL-to-GDSII implementation system.
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Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology (Monday May. 13, 2019)
Cadence today announced that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 28nm FD-SOI (28FDS) process technology.
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ClioSoft Achieves TUV SUD Certification in Support of Automotive ISO 26262 Standard (Friday May. 10, 2019)
ClioSoft today announced that it has achieved Tool Confidence Level 1 (TCL1) certification from TÜV SÜD, enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive functional safety requirements.
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Cadence Delivers Smart JasperGold Formal Verification Platform (Tuesday May. 07, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the third-generation Cadence® JasperGold® Formal Verification Platform, featuring machine learning technology and core formal technology enhancements.
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Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores (Wednesday May. 01, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys and Arm have expanded their collaboration to deliver QuickStart Implementation Kits (QIKs) supporting Synopsys' Fusion Compiler™ solution, the industry's only fully-integrated RTL-to-GDSII implementation system.
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eSilicon Signs Multi-Year Agreement with Google Cloud (Monday Apr. 29, 2019)
eSilicon announced today the signing of a multi-year agreement with Google Cloud to move all of its ASIC and IP design to Google Cloud Platform (GCP) this calendar year.
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Synopsys Design Platform Certified for TSMC's Innovative SoIC Chip Stacking Technology (Wednesday Apr. 24, 2019)
Synopsys, Inc. today announced that the Synopsys Design Platform has been certified for TSMC's latest System-on-Integrated-Chips (TSMC-SoIC™) 3D chip stacking technology.
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Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology (Wednesday Apr. 24, 2019)
Full suite of Cadence digital and signoff, custom/analog, and IC package and PCB analysis tools optimized for TSMC SoIC chip stacking technology
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TSMC Certifies Synopsys' Digital and Custom Design Platforms on TSMC 5nm FinFET Process Technology (Monday Apr. 22, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified both the Synopsys digital and custom design platforms on TSMC's latest production-ready Design Rule Manual (DRM) for its industry-leading 5-nanometer (nm) FinFET process technology.
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Desay SV Standardizes on Synopsys Virtualizer Virtual Prototyping Solutions (Monday Apr. 22, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Desay SV has adopted its Virtualizer™ virtual prototyping solution to accelerate software development of next-generation automotive systems.
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Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design (Monday Apr. 22, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation system-on-chip (SoC) designs for mobile, high-performance computing (HPC), 5G and artificial intelligence (AI) applications on TSMC’s 5nm FinFET process technology.
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Arm China selects Mentor's Questa Verification Solution to enhance power efficiency and speed development of MCU designs (Friday Apr. 19, 2019)
Continuing to expand its functional verification footprint across high-growth markets and applications, Mentor, a Siemens business, today announced that Arm China has selected Mentor’s Questa™ Simulation with Power Aware verification solution to handle critical tasks in the development of next-generation, low-power microcontroller (MCU) cores.
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Cadence Unveils Clarity 3D Solver, Delivering Unprecedented Performance and Capacity for System Analysis and Design (Wednesday Apr. 03, 2019)
Cadence today entered the fast-growing system analysis and design market with the announcement of the Cadence® Clarity™ 3D Solver, which delivers gold-standard accuracy with up to 10X faster simulation performance and unbounded capacity compared to legacy field solver technology.
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Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP (Wednesday Apr. 03, 2019)
Menta SAS, a provider of embedded FPGA (eFPGA) Intellectual Property (IP), today announced a collaboration with Mentor, a Siemens business, to provide High-Level Synthesis (HLS) of the industry’s most flexible eFPGA technology.