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Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
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Cadence Extends Cloud Leadership with New CloudBurst Platform for Hybrid Cloud Environments (Monday Apr. 01, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the availability of the new Cadence® CloudBurst Platform for hybrid cloud environments, providing customers with fast and easy access to pre-installed Cadence design tools in a ready-to-use cloud environment built on either Amazon Web Services (AWS) or Microsoft Azure.
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Cadence Digital Implementation and Parasitic Extraction Tools Enabled for Samsung Foundry Gate-All-Around Technology (Monday Apr. 01, 2019)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the Cadence® Innovus™ Implementation System and Quantus™ Extraction Solution are now enabled for the Samsung Foundry Gate-All-Around (GAA) technology.
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Cadence Collaborates with Northrop Grumman on Chip Design (Thursday Mar. 28, 2019)
Cadence today announced that it is working with Northrop Grumman on advanced-node system-on-chip (SoC) projects, enabling the delivery of high-quality, high-performance SoCs. Cadence® system and verification, digital and signoff, custom/analog and packaging tools, as well as IP solutions, have supported a shortened product development cycle and advanced-node tapeouts.
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Synopsys Announces Collaboration with Samsung Foundry to Offer Secure and Scalable Environment on the Cloud for IC Design and Verification (Wednesday Mar. 27, 2019)
Synopsys today announced it has collaborated with Samsung Foundry to provide a secure, scalable cloud-based IC design and verification environment on the Synopsys Cloud Solution for designers using Samsung Foundry's cutting-edge process technology.
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Synopsys Fusion Design Platform Extends Leadership at 7nm, Surpasses 100-Tapeout Milestone in First Year (Wednesday Mar. 20, 2019)
Synopsys today announced that its Fusion Design Platform™ has achieved a significant 7-nanometer (nm) milestone surpassing 100 tapeouts in the first year, driven by customers realizing 20 percent better quality-of-results (QoR) and more than 2X time-to-results (TTR) speed-up.
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Synopsys Unveils TestMAX Family of Products to Address Critical and Evolving Test Challenges (Wednesday Mar. 20, 2019)
Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the Synopsys TestMAX™ family of products with innovative test and diagnosis capabilities for all digital, memory, and analog portions of a semiconductor device.
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Synopsys Unveils IC Validator NXT to Cut Physical Signoff Cycle by 2X (Monday Mar. 18, 2019)
Synopsys, Inc. today announced its next-generation IC Validator NXT physical verification solution that enables design teams to cut their physical signoff cycle by 2X for advanced technology nodes.
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Synopsys' Fusion Compiler Enables Renesas to Accelerate Delivery of Next-Generation Automotive Designs (Thursday Mar. 14, 2019)
Synopsys today announced that Renesas Electronics Corporation has deployed Synopsys' Fusion Compiler™ RTL-to-GDSII implementation solution for its high-performance automotive system-on-chips (SoCs) and mission-critical microcontrollers (MCUs) to accelerate broad market access to next-generation automotive designs.
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Latest Release of Synopsys' Design Compiler NXT is Ready for Broad Availability (Wednesday Mar. 13, 2019)
Synopsys today announced the availability of Design Compiler® NXT, the latest innovation in the Design Compiler family of RTL synthesis products.
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TRUECHIP Introduces TruEYE -The Debug GUI - A Unique tool for design & verification (Monday Feb. 25, 2019)
Truechip, the Verification IP Specialist, today announced that it has introduced the commercial version of a unique debug GUI for design & verification industry named as TruEYE. This announcement coincides with the DVCon US 2019 where Truechip is the Silver Sponsor to the event.
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Cadence Tools and IP Optimized for New Arm Neoverse N1 Platform to Advance the Cloud-to-Edge Infrastructure Market (Wednesday Feb. 20, 2019)
Cadence today announced that its tools and IP have been optimized to support the new Arm® Neoverse™ N1 platform to accelerate the transformation of a scalable cloud-to-edge infrastructure.
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Synopsys Fusion Design Platform Enables Successful Tapeout of Samsung Foundry's Industry-first Gate-All-Around Transistor SoC (Wednesday Feb. 20, 2019)
Synopsys today announced that Synopsys' Fusion Design Platform™, including the IC Compiler™ II place-and-route system, has enabled the successful tapeout of Samsung Foundry's industry-first gate-all-around (GAA) system-on-chip (SoC) test chip comprising several high-performance, multi-core subsystems.
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Xpeedic's IRIS Qualified on GLOBALFOUNDRIES 12LP Process for High-Performance Applications (Wednesday Feb. 20, 2019)
Xpeedic Technology today announced that its 3D full-wave electromagnetic (EM) simulation tool, IRIS, has been qualified on GLOBALFOUNDRIES' 12nm Leading-Performance (12LP) process technology.
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Cadence Selected as Primary EDA Tool Vendor by GLOBALFOUNDRIES (Friday Feb. 15, 2019)
Cadence today announced that GLOBALFOUNDRIES (GF), has chosen Cadence as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects.
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Graphcore leverages Mentor DFT solutions to speed time to market for innovative AI acceleration chip (Thursday Feb. 07, 2019)
Mentor, a Siemens business, today announced that artificial intelligence (AI) semiconductor innovator Graphcore (Bristol, U.K.) successfully met its silicon test requirements and achieved rapid test bring-up on its Colossus Intelligence Processing Unit (IPU) by using Mentor’s Tessent™ product family.
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Silicon Creations Relies on Silvaco's Custom Design Flow for New Advanced FinFET Designs (Monday Jan. 28, 2019)
Silicon Creations, a supplier of high-performance semi-custom analog and mixed-signal intellectual property (IP), and Silvaco Inc., a leading supplier of EDA software and design IP, today announced that Silvaco's EDA tools have been successfully integrated into Silicon Creations most advanced FinFET design flow for IC designs.
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Mentor's Catapult HLS enables Chips&Media to deliver deep learning hardware accelerator IP in half the time (Wednesday Jan. 16, 2019)
Mentor®, a Siemens business, today announced that Chips&Media™ has successfully deployed Mentor’s Catapult™ HLS Platform to design and verify their c.WAVE computer vision IP for detecting objects in real time, using a deep neural network (DNN) algorithm.
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zGlue Takes Moore's Law Beyond the Possibilities of System-on-Chips with Custom Chips on Demand (Monday Jan. 14, 2019)
zGlue, Inc., a custom-chips-on-demand company, today released its cloud-based chip design software ChipBuilder, and announced the launch of the industry's first multi-project 3D-IC prototyping service in partnership with TSMC and ASE
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Silicon Valley Company unveils the first automotive architecture exploration platform with Time-Sensitive Networking (IEEE802.1Q) protocol (Thursday Jan. 10, 2019)
Mirabilis Design announced the immediate availability of Time-Sensitive Networking (IEEE802.1Q) protocol in the VisualSim AI-based Automotive Architecture Exploration Platform, an unique library of network protocols, electronics, software components and a high-performance modeling and simulation platform.
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Weebit Nano and Silvaco Form Development Program Partnership to Create ReRAM Models and Design Tools (Thursday Jan. 10, 2019)
Weebit Nano (ASX: WBT), the Israel-based semiconductor company seeking to develop and commercialise the next generation of memory technology, and Silvaco, a leading global provider of software, IP and services for designing chips and electronic systems for semiconductor companies, today announced their Development Program Partnership to model the electrical behavior of SiOx ReRAM devices.
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Innovium Selects Synopsys' IC Validator for Physical Signoff (Thursday Jan. 10, 2019)
Synopsys today announced that Innovium, Inc., a leading provider of networking solutions for data centers, has adopted the Synopsys IC Validator tool for physical signoff. Innovium deployed IC Validator on their flagship 12.8 terabit-per-second (Tbps) throughput TERALYNX switch.
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Industry Leaders Collaborate with Synopsys on Modeling Standards to Address Design Down to 2nm (Wednesday Dec. 19, 2018)
Synopsys today announced that the Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB) have ratified new modeling constructs to address timing and parasitic extraction challenges at process nodes down to two nanometers (nm).
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Cadence Timing Signoff Tools Enable MaxLinear to Deliver Industry's First 400Gbps PAM4 SoC on 16FF Process (Monday Dec. 10, 2018)
Cadence today announced that MaxLinear, Inc., used Cadence® timing signoff tools to successfully deliver the MxL935xx Telluride device, the industry’s first 400Gbps PAM4 system on chip (SoC) using 16FF process technology.
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Synopsys and imec Demonstrate Accelerated Modeling of Innovative Complementary FET (CFET) Technology (Monday Dec. 10, 2018)
Synopsys, Inc. (Nasdaq: SNPS) announced today another milestone in its longstanding partnership with imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, with the successful completion of the first comprehensive sub-3 nanometer (nm) parasitic variation modeling and delay sensitivity study of complementary FET (CFET) architectures.
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Valtrix STING DV Platform Selected by AI Chipmaker Esperanto Technologies (Friday Dec. 07, 2018)
Valtrix Technologies, an EDA company delivering Design Verification (DV) solutions for the semiconductor industry, announced that Esperanto Technologies has selected Valtrix’s STING DV Platform for design verification of its energy-efficient semiconductor solutions for artificial intelligence (AI) and machine learning (ML) based on the open standard RISC-V instruction set architecture.
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Imperas and Valtrix announce partnership for RISC-V Processor Verification (Monday Dec. 03, 2018)
Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced the partnership with Valtrix Systems for advanced RISC-V Processor test and validation.
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Cadence Delivers Advanced Packaging Reference Flow for Samsung Foundry Customers (Wednesday Nov. 14, 2018)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that the complete Cadence® advanced packaging design and analysis tool flow is certified by Samsung Foundry for Fan-Out Panel-Level-Packaging (FO-PLP) and silicon-interposer 2.5D package.
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Imperas Empowers RISC-V Community with riscvOVPsim (Wednesday Nov. 07, 2018)
Imperas leading commercial simulation technology available for free with RISC-V Open Virtual Platform Simulator (riscvOVPsim™) for RISC-V software development, compliance and DV test developments
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New Mentor Symphony platform addresses nanometer-scale SoC mixed-signal verification challenges (Wednesday Nov. 07, 2018)
Mentor, a Siemens business, today announced the availability of the Symphony Mixed-Signal Platform, which combines the leading foundry-certified Analog FastSPICE (AFS™) circuit simulator with industry-standard HDL simulators to provide fast and accurate verification of complex nanometer-scale mixed-signal integrated circuits (ICs).
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Synopsys Extends Synthesis Leadership with Next-Generation Design Compiler (Tuesday Nov. 06, 2018)
Synopsys, Inc. (Nasdaq: SNPS) today announced Design Compiler® NXT, the latest innovation in the Design Compiler family of RTL Synthesis products, extending the market-leading synthesis position of Design Compiler Graphical.