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Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
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Synopsys Design Platform Certified by GLOBALFOUNDRIES for 22nm FD-SOI Process Technology (Wednesday Sep. 20, 2017)
Synopsys today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX™) process, ensuring designers achieve optimized implementation and predictable signoff results using industry leading digital design tools.
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Intel Custom Foundry Certifies Synopsys Design Platform for Intel's 22nm FinFET Low Power Process Technology (Tuesday Sep. 19, 2017)
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Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology (Tuesday Sep. 19, 2017)
Cadence today announced that its full-flow digital and signoff tools and its custom/analog tools have been certified/enabled for the Intel® 22FFL (FinFET Low-Power) process, which provides up to 100X lower leakage and a 2.5X active power reduction compared with its previous 22GP (general purpose) offering.
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Cadence Introduces the Conformal Smart Logic Equivalence Checker (Thursday Sep. 14, 2017)
Cadence today announced the Cadence® Conformal® Smart Logic Equivalence Checker (LEC), the next-generation equivalence checking solution that delivers a significant improvement in equivalence checking runtime with minimal user effort.
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Synopsys IC Compiler II Certified for TSMC's Advanced 7-nm FinFET Plus Node (Monday Sep. 11, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified the Synopsys Design Platform for the latest Design Rule Manual (DRM) of its 7-nm FinFET Plus process technology.
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Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation (Monday Sep. 11, 2017)
Cadence today announced its collaboration with TSMC to advance 7nm FinFET Plus design innovation for mobile and high-performance computing (HPC) platforms.
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Cadence Tools and Flows Achieve Production-Ready Certification for TSMC's 12FFC Process (Monday Sep. 11, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Cadence® digital, signoff and custom/analog tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for customers seeking to deploy 12FFC.
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Synopsys' IC Compiler II Completes Certification for TSMC's 12-nm Process Technology (Monday Sep. 11, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified IC Compiler™ II place-and-route system and Synopsys Design Platform for the V1.0 production of its latest 12-nanometer (nm) FinFET process technology.
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Solido launches PVTMC Verifier from its Machine Learning Labs (Thursday Sep. 07, 2017)
Solido Design Automation today announced the launch of PVTMC Verifier. PVTMC Verifier uses machine learning to thoroughly verify designs across the complete spectrum of process variation and operating conditions, enabling users to reduce their design cycle time, produce more competitive chips, and prevent silicon failures.
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Samsung SARC Selects Synopsys as Primary Verification Solution for Advanced Mobile Processor Designs (Tuesday Sep. 05, 2017)
Synopsys today announced that Samsung SARC has selected the Synopsys Verification Continuum™ platform as its primary verification solution for their high-performance, low-power CPU, GPU and system IP designs.
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Mentor extends functional safety assurance program to key design, verification and analog/mixed signal products (Thursday Aug. 31, 2017)
Mentor, a Siemens business, has further expanded its successful Mentor Safe functional safety program to include the Catapult® High-Level Synthesis (HLS) platform and a host of advanced analog/mixed-signal (AMS) IC verification products, including Eldo® and the Analog FastSPICE™ (AFS™) Platform.
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Cadence Full-Flow Digital and Signoff and Verification Suite Optimized to Support Arm Cortex-A75 and Cortex-A55 CPUs and Arm Mali-G72 GPU (Monday Aug. 07, 2017)
Cadence today announced that its full-flow digital and signoff tools and the Cadence® Verification Suite have been optimized to support Arm® Cortex®-A75 and Cortex-A55 CPUs, based on Arm DynamIQ™ technology, and the Arm Mali™-G72 GPU, the latest offerings from Arm for premium mobile, machine learning, and consumer devices.
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Artificial Machines Standardizes on Mentor EDA Design Solutions to Develop Smart Machine IP (Thursday Aug. 03, 2017)
Mentor, a Siemens business, today announced that Artificial Machines, a leading smart machine design company that empowers its customers with cutting-edge SMART machine intellectual property, has standardized on Mentor electronic design automation (EDA) design solutions.
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UltraSoC delivers industry's first debug and analytics solution for ARM's AMBA 5 CHI Issue B coherency architecture (Wednesday Aug. 02, 2017)
UltraSoC, the leading developer of embedded analytics technology, today announced the general availability of full debug and monitoring IP for ARM’s recently announced AMBA 5 Coherent Hub Interface (CHI) Issue B.
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Blue Pearl Software Streamlines RTL Verification for Xilinx All Programmable FPGAs and SoCs (Friday Jul. 28, 2017)
The release extends Blue Pearl’s leadership in RTL verification of Xilinx® All Programmable FPGAs and SoCs with direct integration inside the Vivado® Design Suite accelerating setup, analysis and debug of FPGA IP and designs.
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MediaTek Standardizes on Synopsys' HAPS-80 Prototyping System (Wednesday Jul. 26, 2017)
Synopsys today announced that MediaTek, a leading fabless semiconductor company, has adopted Synopsys' HAPS®-80 prototyping system, part of the Verification Continuum™ Platform, for their broad portfolio of next generation system-on-chips (SoCs).
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Cadence Genus Synthesis Solution Enables Toshiba to Complete a Successful ASIC Tapeout with a 2X Logic Synthesis Runtime Improvement (Thursday Jul. 20, 2017)
Cadence today announced that Toshiba Electronic Devices & Storage Corporation used the Cadence® Genus™ Synthesis Solution to complete a successful ASIC design tapeout.
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Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM (Tuesday Jul. 18, 2017)
Cadence today announced that the Cadence® Functional Safety Verification Solution was adopted by ROHM CO., Ltd. in its design flow for ISO 26262-compliant ICs and LSIs for the automotive market.
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Kyocera Selects Synopsys VC Formal for High-Performance Property Verification (Wednesday Jun. 28, 2017)
Synopsys today announced that Kyocera, a leading supplier of telecommunications equipment, information equipment, semiconductor packages and electronic components, has selected Synopsys' VC Formal™ solution for high-performance formal property verification of their Multi-Functional Product (MFP) designs.
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Dolphin Integration Selects Silvaco Variation Manager eXtreme Memory Analysis for SRAM Design At Advanced Nodes (Wednesday Jun. 28, 2017)
Silvaco today announced that Dolphin Integration, a leading provider of power- and density-optimized memory silicon IP, has selected Silvaco’s Variation Manager™ for full memory statistical analysis to perform reliability qualification on SRAM memories designed using advanced process technologies.
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Cadence Expands Online Tool Access for ARM DesignStart Customers to Accelerate SoC Design Delivery (Tuesday Jun. 20, 2017)
Cadence today announced expanded support for the enhanced ARM® DesignStart™ program, including the newly added ARM Cortex®-M3 processor and the ARM CoreLink™ SDK-100 System Design Kit, which includes the fully verified CoreLink SSE-050 subsystem, enabling engineers to further accelerate the delivery of mixed-signal internet of things (IoT) designs.
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Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node (Tuesday Jun. 20, 2017)
Cadence today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology.
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Spectral announces "Enablement Package" for Silicon proven Reference SRAM designs on advanced process nodes (Tuesday Jun. 20, 2017)
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ANSYS And Synopsys To Partner In Accelerating Robust Design Optimization For Next Generation High-Performance Computing, Mobile And Automotive Products (Monday Jun. 19, 2017)
ANSYS and Synopsys will enable customers to accelerate the next generation of high-performance computing, mobile and automotive products thanks to a new partnership that will tightly integrate ANSYS' power integrity and reliability signoff technologies with Synopsys' physical implementation solution for in-design usage.
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Runtime Accelerates Time to Market with New License Allocation Management Solution (Monday Jun. 19, 2017)
Runtime, a leading provider of infrastructure and design optimization software solutions, introduced a new license allocation management solution, LicenseAllocator. LicenseAllocator is a policy-driven and real-time license allocation management solution that enables the seamless sharing of software licenses among users from multi-sites in the context of project priorities.
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Toshiba Selects Synopsys VC Formal Verification Solution (Thursday Jun. 15, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Toshiba has deployed Synopsys' VC Formal™ solution as their SystemVerilog Assertion (SVA) based formal verification solution.
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Mentor Verification Is First to Deliver Portable Stimulus Technology Across the Full Enterprise Verification Platform (Thursday Jun. 15, 2017)
Mentor, a Siemens business, today announced it has expanded its portable test and stimulus technology across its full Enterprise Verification Platform™ to enable users to verify more with the same resources.
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Mentor Achieves ISO 26262 Qualification for Oasys-RTL, Nitro-SoC and FormalPro Tool Reports (Wednesday Jun. 14, 2017)
Mentor, a Siemens business, has further expanded its Mentor Safe functional safety assurance program by qualifying the ISO 26262 compliance of documentation for its Oasys-RTL Physical RTL Synthesis, Nitro-SoC Place and Route, and FormalPro Logic Equivalency Checker products.
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Magillem EDA solution selected by Renesas for design automation, IP packaging and content generation (Monday Jun. 12, 2017)
Magillem, a leading provider of software solutions for complex front end design and documentation flow, today announced that Renesas Electronics Corporation has adopted Magillem’s EDA solution for its design automation, IP packaging and content generation.
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Mentor Catapult HLS Enables Stream TV's R&D Group SeeCubic to Develop Glasses-Free 3D Digital Display IP (Thursday Jun. 08, 2017)
Mentor, a Siemens business, today announced that Stream TV Networks’ R&D center SeeCubic has successfully used Mentor’s Catapult® High-Level Synthesis (HLS) tool to create an IP block that converts 2D or stereo-3D video content to the Ultra-D™ format.