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STMicroelectronics Standardizes on Synopsys VC Formal for Faster Verification Closure of Leading Microcontroller Designs (Wednesday Jun. 07, 2017)
Synopsys, Inc. (Nasdaq:SNPS), today announced that STMicroelectronics selected and standardized on Synopsys VC Formal, as their formal verification solution for advanced microcontroller designs.
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Mentor Ushers in New Era of C++ Verification Signoff with New Catapult Tools and Solutions (Tuesday Jun. 06, 2017)
Mentor, a Siemens business, today announced three new tools - Catapult® Coverage, Catapult Design Checks and SLEC® HLS – and enhancements to Catapult HLS.
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OneSpin Solutions Unveils its Comprehensive Safety Critical Solution for Automotive, Other Mission-Critical Applications (Thursday Jun. 01, 2017)
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Cadence Announces VirtualBridge Adapter for Palladium Z1 Emulator to Accelerate Software Bring-Up Time by Up to Three Months (Wednesday May. 31, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the release of the new VirtualBridge™ Adapter, a virtual emulation technology that accelerates software bring-up in pre-silicon verification versus RTL simulation.
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New Cadence Virtuoso System Design Platform Provides Seamless Design Flow Between IC, Package and Board (Wednesday May. 31, 2017)
Cadence today announced the Cadence® Virtuoso® System Design Platform, a formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro® and Sigrity™ technologies.
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Synopsys ZeBu Server Emulation System Selected by Konica Minolta (Tuesday May. 30, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that its ZeBu® Server emulation system has been selected and deployed by Konica Minolta as their standard hardware platform for verification and early software bring-up on their multi-function printer (MFP) system-on-chip (SoC) designs.
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Synopsys Design and Verification Tools Enable Successful Tape-outs by Early Adopters of New ARM Cortex-A75, Cortex-A55 and Mali-G72 Cores (Monday May. 29, 2017)
Synopsys today announced that early collaboration with ARM on its latest IP targeted at artificial intelligence applications, including the ARM® Cortex®-A75 and Cortex-A55 Central Processing Units (CPUs), the first based on ARM DynamIQ™ technology, and the ARM Mali™-G72 Graphics Processing Unit (GPU), has resulted in successful early adopter tape-outs in advanced FinFET process technologies using Synopsys' Design Platform and Verification Continuum™ Platform.
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Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology (Thursday May. 25, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its custom/analog tools and full-flow digital and signoff tools have achieved certification for the process design kit (PDK) and foundation library for the Samsung Electronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI, process technology.
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Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung's 7LPP and 8LPP Process Technologies (Thursday May. 25, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its digital, signoff and custom/analog tools are enabled on Samsung Electronics’ 7LPP and 8LPP process technologies.
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Synopsys Custom Compiler Certified by Samsung for 28FDS Process Technology (Wednesday May. 24, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Synopsys' custom design platform has been certified by Samsung Electronics for its 28FDS (FD-SOI) process technology.
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Synopsys Enables the Next Wave of Design Innovation on Samsung's Latest Foundry Processes, 8LPP and 7LPP (Wednesday May. 24, 2017)
Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Electronics Co., Ltd. has enabled the Synopsys Design Platform for Samsung's 8LPP (Low-Power Plus) and 7LPP process technologies.
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Synopsys IC Validator Certified by Samsung for 10LPP Process Technology Physical Signoff (Wednesday May. 24, 2017)
Synopsys today announced that its IC Validator physical signoff solution has been certified by Samsung Electronics for physical signoff of all designs using the 10LPP process technology.
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Mentor Announces Availability of Tools and Flows for Samsung 8LPP and 7LPP Process Technologies (Wednesday May. 24, 2017)
Mentor, a Siemens business, today announced in collaboration with Samsung Electronics that a wide range of Mentor design and verification tools and flows have been enabled for Samsung's 8LPP process technology.
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Acacia Communications Reduces Simulation Regression Turnaround Time by 2X Using Synopsys VCS Fine-Grained Parallelism Technology for High-Speed Optical Interconnect SoCs (Thursday May. 18, 2017)
Synopsys today announced that Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by 2X.
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Cadence Expands JasperGold Platform for Advanced Formal-Based RTL Signoff (Tuesday May. 16, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the expansion of its JasperGold® Formal Verification Platform with the introduction of the JasperGold Superlint and Clock Domain Crossing (CDC) Apps, advanced formal-based technologies that address register-transfer level (RTL) signoff requirements.
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Cadence and MathWorks Announce New Integration to Accelerate Data Mining and Analytics (Tuesday May. 16, 2017)
Cadence today announced it has expanded its partnership with MathWorks through a new integration between the Cadence® Virtuoso® Analog Design Environment (ADE) Product Suite and MATLAB®, enabling customers to accelerate processing of large data sets when verifying custom, RF and mixed-signal designs.
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HHGrace and Empyrean Continue Their Cooperation on Local EDA Tools to Facilitate IP Design (Friday Apr. 28, 2017)
HHGrace and Empyrean, jointly announce that HHGrace has adopted and successfully taped out Empyrean’s high-speed, high-precision parallel simulator ALPS™.
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Amlogic Reduces HW/SW Integration Time for Multimedia SoCs by Two Months Using the Cadence Protium S1 FPGA-Based Prototyping Platform (Wednesday Apr. 26, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Amlogic has adopted the new Cadence® ProtiumTM S1 FPGA-Based Prototyping Platform to deliver multimedia system-on-chip (SoC) designs to market faster.
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Wave Computing Accelerates its Machine Learning Software Bring-up by 12 Months Using Synopsys ZeBu Server Emulation System (Wednesday Apr. 26, 2017)
Synopsys today announced that Wave Computing has selected Synopsys ZeBu® Server-3 system as the emulation solution for early software bring-up and development for its Dataflow Processing Unit (DPU) architecture.
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Accelize Integrates Amazon EC2 F1 Instance into its QuickPlay/QuickStore Framework (Thursday Apr. 20, 2017)
Accelize today announces that it is integrating the Amazon Elastic Compute Cloud (Amazon EC2) F1 instance into its QuickPlay®/QuickStore® framework. With this support, customers and partners can leverage the QuickPlay Software Defined FPGA development platform and its associated catalog of highly efficient 3rd party IP cores to seamlessly create Amazon FPGA Images (AFIs) regardless of their FPGA expertise.
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Mentor Graphics expands formal verification's reach with new cross-platform GUI and apps for sequential logic equivalence checking and CDC gate-level analysis (Thursday Apr. 20, 2017)
Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and verification engineers with the ability to more easily perform exhaustive formal verification analysis.
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Silicon Creations Selects Mentor Graphics Software for High-Performance Analog and Mixed-Signal IP Verification (Thursday Apr. 13, 2017)
Mentor, a Siemens business, today announced that Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), has selected Mentor software for circuit, functional, and physical verification of its complex pre-layout and post-layout analog and mixed-signal IP.
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Cadence Launches the Pegasus Verification System, a Massively Parallel Physical Signoff Solution (Wednesday Apr. 12, 2017)
Cadence today announced the Pegasus™ Verification System, a massively parallel, cloud-ready physical verification signoff solution that enables engineers to deliver advanced-node ICs to market faster.
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Mentor Announces Availability of Qualified Reference Flow to Help Designers Achieve Success with Samsung 14LPP Process Technology (Wednesday Apr. 12, 2017)
Mentor, a Siemens business, today announced the availability of a qualified reference flow comprising a wide range of design implementation, verification, and test tools and flows optimized for Samsung Electronics’ 14LPP (Low Power Plus) process technology.
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Solido Launches Machine Learning (ML) Characterization Suite (Thursday Apr. 06, 2017)
Solido Design Automation, a leading provider of variation-aware design and characterization software, today announced the immediate release of its Machine Learning (ML) Characterization Suite.
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Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes (Wednesday Apr. 05, 2017)
Cadence today announced the release of the new Virtuoso® Advanced-Node Platform supporting advanced 7nm designs. Through collaboration with early 7nm FinFET customers, Cadence has expanded the Virtuoso custom design platform with innovative new capabilities to manage design complexity and process effects introduced with this advanced-node process.
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Cadence Voltus IC Power Integrity Solution Enables Juniper Networks to Achieve First-Pass Silicon Success for its Largest Networking SoC (Wednesday Apr. 05, 2017)
Cadence today announced that Juniper Networks achieved first-pass silicon success for its largest system-on-chip (SoC) design with hundreds of millions of instances on the latest FinFET process using the Cadence® Voltus™ IC Power Integrity Solution.
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Synopsys' IC Validator Used for Physical Sign-Off on More Than 100 FinFET Production Tapeouts (Tuesday Mar. 28, 2017)
Synopsys today announced that its IC Validator physical verification product has been successfully used for signoff on more than 100 tapeouts at advanced FinFET nodes.
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Renesas Accelerates IoT Design Using the Cadence Perspec System Verifier (Wednesday Mar. 22, 2017)
Cadence today announced that Renesas has used the Cadence® Perspec™ System Verifier to verify its new micro-controller unit (MCU) design for internet of things (IoT) applications.
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Space Codesign to Announce SpaceStudio V3 to Facilitate Functional Verification and Validation of Embedded Systems (Tuesday Mar. 21, 2017)
Space Codesign Systems, a leading provider of an end-to-end automated hardware/software co-design software solution - from high-level functional specification to architectural and RTL (Registered Transfer Level) coding phase, introduces SpaceStudio version 3.