130nm OTP Non Volatile Memory for Standard CMOS Logic Process
167 Results (161 - 167) |
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Andes Technology and INVECAS Enter Into a High Value Collaboration to Win Designs for GLOBALFOUNDRIES 22FDSOI and 14LPP Processes
Oct. 21, 2015 - Andes Technology and INVECAS today announced a high value collaboration. Andes and INVECAS will develop platforms on GLOBALFOUNDRIES' advanced process nodes enabling customers to reduce their risk and time to market. -
Imec and sureCore collaborate on SRAM Design IP
Mar. 31, 2015 - sureCore Ltd., the low power SRAM IP company, and nanoelectronics R&D center, imec, today announced that they are collaborating on low-power SRAM IP. The collaboration includes the licensing of a set of imec SRAM design IP to sureCore to expand sureCore's IP portfolio and a participation in sureCore. ... -
Common Platform in Preparation for SOI, FinFETs at 10nm
Apr. 09, 2014 - A team of engineers from IBM Microelectronics, Globalfoundries, Samsung, STMicroelectronics and UMC are due to present a 10nm logic platform that supports FinFETs on both bulk CMOS and on silicon-on-insulator wafers. -
Moortec Semiconductor Announces Industry Leading, High Accuracy On-Chip Temperature Sensor Range for Advanced Nodes
Oct. 29, 2013 - Moortec announces its range of high accuracy on-chip temperature sensors for advanced CMOS technologies. This latest range extends Moortec's position as a leading provider of embedded thermal sensors to semiconductor customers worldwide. -
sureCore receives GBP250K SMART Award to prototype its low power SRAM technology
May. 16, 2013 - sureCore Ltd announced that it has secured a Technology Strategy Board SMART award of £250K to help realise the company’s low power SRAM technology in a leading edge next generation silicon process node. -
STMicroelectronics Makes 28nm CMOS Process Available Through CMP
Jun. 16, 2011 - STMicroelectronics and CMP today announced that the CMOS 28nm process from STMicroelectronics is now available for prototyping to universities, research labs and companies through the silicon brokerage services provided by CMP. -
CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP
Oct. 01, 2010 - CEA-Leti and CMP (Circuits Multi Projets ®) announced the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community.