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IP / SOC Products News

• Lattice FPGA IP Support Expands With Multimedia Cores From Art of Silicon (Monday Jul. 24, 2006)
  Art of Silicon Optimizes JPEG IP Cores for the LatticeECP2, LatticeSC & LatticeXP FPGA Devices
  
  
• Virage Logic and MIPS Technologies Introduce New Core-Optimized IP Kits for MIPS32(R) 24K(R), 24KE(TM) and 34K(TM) Core Families in 90nm G Process (Monday Jul. 24, 2006)
  New Kits Enable 24K and 24KE Processor Cores to Achieve Clock Frequencies of Up to 660 MHz
  
  
• ARM Announces AMBA 3 AXI Design Tools And Fabric IP For High-Performance, Power-Efficient SoC Designs (Monday Jul. 24, 2006)
  ARM has secured multiple licensees for the new Fabric IP which enables the rapid assembly of SoC designs
  
  
• ARM Enhances Reference Methodologies With Library Views And Pre-Compiled Rams (Monday Jul. 24, 2006)
  ARM Enhances Reference Methodologies With Library Views And Pre-Compiled Rams
  
  
• Evatronix Releases Updates to R8051XC Microcontroller Cores (Monday Jul. 24, 2006)
  Evatronix S.A., the silicon Intellectual Property (IP) provider, has announced technical updates to its R8051XC microprocessor cores used in a wide range of applications including wireless transmission control chips (supporting ZigBee or Bluetooth protoco
  
  
• Deal enables MOSIS to offer XAP 16-bit processors (Friday Jul. 21, 2006)
  Cambridge Consultants has teamed up with multi-project wafer (MPW) services provider, MOSIS, to enable royalty-free access to their XAP4 and XAP5 16-bit RISC processor cores
  
  
• Parallel processor firm enhances core for HD video (Friday Jul. 21, 2006)
  PACT XPP Technologies AG, a developer of a reconfigurable highly parallel processor, has redesigned its technology to produce the XPP-III version of its architecture and claimed that performance, for the first time, allows high definition video decoding w
  
  
• Infineon to Enter Ultra-Wideband Market with Industry's First Dual-Band RF-CMOS Transceiver Core - Paving the Way for the Converged Entertainment Cell Phone (Wednesday Jul. 19, 2006)
  The dual-band UWB RF-CMOS transceiver core supports both the 3 GHz-to-5 GHz frequency band and the above-6 GHz band up to 9 GHz, as defined in the WiMedia band plan.
  
  
• ARM Releases Next-Generation DDR Memory Solutions To Improve Chip Performance (Wednesday Jul. 19, 2006)
  The expanded ARM® Velocity DDR products are compliant with JEDEC standards for DDR, DDR2, Mobile DDR and GDDR3 SDRAM and support standard CMOS processes on 130-nanometer(nm), 110nm, 90nm and 65nm nodes for leading foundries
  
  
• Celoxica Adds Floating-Point Toolkit to IP Portfolio; Cores Optimized for FPGA-Based Digital Signal Processing & High-Performance Computing Applications (Wednesday Jul. 19, 2006)
  The IEEE 754 compliant libraries support single, double and custom precision Floating-Point. They are fully parameterizable for area, latency and performance optimization across all leading programmable logic architectures and can be tuned to specific app
  
  
• Azuro's PowerCentric Reduces Power Consumption For ARC Configurable Subsystems and Cores by More Than 20 Percent (Wednesday Jul. 19, 2006)
  With the use of Azuro's PowerCentric in existing Cadence, Synopsys or Synplicity design flows, customers of the configurable ARC Media Subsystems and CPU/DSP processors can reduce power consumption of the ARC-Based™ logic by more than twenty percent
  
  
• IP Cores, Inc. Announces Two CCM* Security IP Cores for IEEE 802.15.4 Designs (Monday Jul. 17, 2006)
  IP Cores, Inc. announces silicon IP cores supporting the CCM* encryption mode used in the IEEE 802.15.4 wireless standard. Starting at 6K ASIC gates, CCMZ cores provide an ultracompact solution for an SoC designer working on a IEEE 802.15.4 solution.
  
  
• Silistix Self-Timed Interconnect Solution Adds Support for AXI Bus Protocol (Monday Jul. 17, 2006)
  Silistix, a provider of innovative software for on-chip communications solutions, today announced that they have added support for the on-chip AMBA™ AXI™ bus protocol with Silistix's synthesized self-timed interconnect technology
  
  
• QualCore Logic Adds Line of Temperature Measurement IP to Portfolio; Analog Cores Used to Measure Internal Temperature of ICs (Monday Jul. 17, 2006)
  Analog Cores Used to Measure Internal Temperature of ICs
  
  
• Synopsys 2006.06 Release of DesignWare Library Reduces Area and Delay in IC Designs (Wednesday Jul. 12, 2006)
  Synopsys Expands DesignWare Library With More Than 20 New IP Components
  
  
• IBM and Chartered Team with Synopsys for Mixed-Signal Connectivity IP at 65 NM (Tuesday Jul. 11, 2006)
  Synopsys USB, PCIe, SATA and XAUI PHYs for High-Volume, Low-Power Applications Available for Foundries' Leading-edge Processes
  
  
• IP Cores, Inc. Announces a Family of High-Speed AES/LRW IP Cores Supporting IEEE P1619 Standard (Tuesday Jul. 11, 2006)
  IP Cores, Inc. announces a family of silicon IP cores supporting the new secure storage standard IEEE P1619. Starting at 44K ASIC gates for LRW2-25.6 and delivering up to 70 Gbps throughput with LRW2-128, LRW2 cores provide a flexible and high-performance
  
  
• MathStar, Inc. Announces World's Fastest Reprogrammable JPEG 2000 Encoder for the Field Programmable Object Array(TM) (FPOA(TM)) (Monday Jul. 10, 2006)
  MathStar, Inc., the field programmable object array (FPOA) leader, today announces its JPEG 2000 Encoder Core for the Field Programmable Object Array (FPOA), a new class of high-performance logic platform chips.
  
  
• Cswitch and Denali Team on PCI Express for Configurable Switch Array Chip (Monday Jul. 10, 2006)
  Denali and Cswitch today announced the results of a collaborative effort to deploy Denali's Databahn™ PCI Express core on Cswitch's Configurable Switch Array chip
  
  
• IQ-Analog now offers low power, size efficient wideband Analog Front End for (AFE) for WiMAX, Digital Video Broadcast and 802.11x applications (Thursday Jul. 06, 2006)
  The Rx performance at 10 MHz delivers Signal to Noise Differential ratio (SNDR) > 65 dB and Signal Frequency Differential ratio (SFDR) > 68 dB. With a die area of 1.6 mm2, the combination of throughput performance, low power consumption, and size efficien
  
  
• TaraCom Introduces SerDes/PHY IPs in 90 and 65-Nanometer (Thursday Jul. 06, 2006)
  TaraCom has ported the Serial ATA (SATA) core intellectual core property (IP) for integration into SoC and ASIC designs ranging from XAUI compliant, PCS/PMD functionality of the 10 Gigabit Ethernet XAUI and 10 Gigabit Fibre Channel specs as well as SATA,
  
  
• DAFCA Announces Availability of ClearBlue Debug Infrastructure IP and Software Product Family (Monday Jul. 03, 2006)
  Recently patented technology enables accelerated post-silicon SoC Debug, Diagnosis and Validation.
  
  
• Digital Blocks Announces the Re-launch of its DB8279 Programmable Keyboard / Display Interface IP Core (Friday Jun. 30, 2006)
  Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for embedded processor system designers, today announces the re-launch of its DB8279 Programmable Keyboard / Display Interface core.
  
  
• Synopsys Introduces Validated USB 2.0 nanoPHY IP for TSMC'S Nexsys 90-LP Process (Wednesday Jun. 28, 2006)
  Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced the immediate availability of the DesignWare® USB 2.0 nanoPHY intellectual property (IP) for Taiwan Semiconductor Manufacturing Company's (TSMC's) Nexsys 90-nan
  
  
• Denali's Databahn Memory Controller IP Supports Cadence Encounter Synthesis (Wednesday Jun. 28, 2006)
  Cadence Design Systems, Inc. and Denali Software, Inc. today announced support for Cadence® Encounter® RTL Compiler global synthesis on Databahn(TM) memory controller products.
  
  
• Avago Advances Its ASIC Technology to the Next Generation: Proves High-Performance 12.5 Gbps SerDes Core in 65 Nm CMOS Process (Monday Jun. 26, 2006)
  This milestone advances the state of SerDes (Serialization/Deserialization) ASIC core design from today's mainstream 90 nm to 65 nm process technology.
  
  
• Silistix Partners with Tensilica to Develop a Demonstration Test Chip for Portable Multimedia Applications (Monday Jun. 26, 2006)
  The CMOS chip will demonstrate the ability of the Silistix CHAIN self-timed interconnect technology to work with high-performance processor cores from Tensilica along with additional silicon cores from Denali and sci-worx at a 65nm process node
  
  
• Chipidea Launches New Line of CMOS Radio Frequency IP Platforms (Monday Jun. 26, 2006)
  Chipidea®, the world leader in analog/mixed-signal merchant technology, today announced the expansion of its radio frequency (RF) intellectual property (IP) line with the release of two new cores designed to speed the development of video-enabled handheld
  
  
• ARC and Cadence Announce Optimized Integration of Encounter Digital IC Platform with ARChitect Processor Configurator (Monday Jun. 26, 2006)
  Using ARChitect, ARC licensees now can produce RTL, synthesis and floorplanning scripts that are tuned to the Encounter reference methodology. This will help the system-on-chip (SoC) designer better anticipate the behavior of electrical signals and ensure
  
  
• IMEC software-defined radio concept compliant with 3GPP-LTE (Monday Jun. 26, 2006)
  IMEC, Europe's leading independent nanoelectronics and nanotechnology research institute, shows at Cannes on the air 3GPP-LTE compliant data transmission, from a first FPGA-based hardware-software prototype of its flexible air interface (FLAI) platform