Major of CMOS Image Sensor (CIS) column A/D converter is integrating A/D converter, but it has limited to be high-bits. The CI00101IP can realize 14bits column A/D converter by little increase in a circuit scale for use of "Warp & Walk(Successive Approximation & Single Slope)" algorithm.
- Power Voltage : 3.3V Analog (or 2.8V) 1.8V Analog/Digital Power Supply
- Internal Clock : 108MHz (max:250MHz)
- A/D Format : CURIOUS Warp & Walk format (Successive Approximation & Single Slope)
- A/D Resolution : 14bit
- A/D Conversion Time : 30uSec(max:16uSec)/Column
- Power Consumption : 20uW/Column
- Column Pitch : 7.2um (max:4.5um)
- V-FPN is nothing and random noise is small, to use High-Gain amplifier for first stage.
- This IP is used in Asian CIS(CMOS Image Sensor) LSI.
- This Warp&Walk technology is our original.
- This IP can add our Intarface IP(MIPI-DPHY,sub-LVDS,etc).
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP or Custom-CIS of used this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- 1) Circuits data
- 2) Simulation enviloment files
- 3) IBIS or Hspice netlist file