This IP is a HDMI 1.4 / MHL 2.0 dual mode Tx digital IP. It is a highly configurable IP featuring xvYCC and the possibility to either bypass unused video processing modules or completely remove unused modules from the design. Furthermore, the audio input can be configured to either having a 32 bit wide parallel interface (which can be connected e.g. to a RAM) or the common serial interface or serial interface.
- Design flow scripts for Synthesis, CDC, Linting, Formality, etc
- Documents including design spec, integration guideline etc.
- RTL source code
- Simulation environment