The DesignWare® ARC® Vector Floating Point Unit (FPU) option for the ARC EV processors adds performance-efficient hardware acceleration to enable floating point math acceleration. The vector FPU (VFPU) can be integrated into the EV6x embedded vision processor's vector DSP core. The VFPU is IEEE 754-compliant for ADAS applications, self-driving vehicles, powertrain, and automotive ADAS sensor fusion (linear algebra). Combined with the ARC MetaWare EV Development Toolkit, the VFPU offers performance levels of up to 328 Gigaflops for single precision operations and 655 Gigaflops for half precision operations.
- Optimized for high frame-rate and video resolution embedded vision applications
- Integrates 32-bit scalar core, 512-bit vector DSP, and optional CNN engine
- 12 configurations available, with 1, 2 or 4 vision CPUs and CNN performance options
- CNN engine delivers up to 4.5 TeraMACs/ sec and offers power efficiency of up to 2,000 GMACs/sec/W
- CNN engine supports both coefficient and feature map compression/decompression
- Works with all host processors for vision offload
- High productivity MetaWare EV Development Toolkit supports OpenCV, OpenVX and OpenCL C
- The DesignWare EV61, EV62, and EV64 Processors and optional CNN engine are delivered as Verilog HDL in the ARChitect IP Library. The HDL is configured and output from the ARChitect IP Configurator tool.
- To test that the product performs as expected, a basic testbench of Customer Confidence Tests (CCT) is included.