The S3REG5033TJ180 is a regulator circuit which has been designed to provide 1.8V with a load current of up to 50mA, having a low area and high PSRR.
The S3REG5033TJ180 is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop operation, while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads, e.g. pipeline ADCs.
The S3REG5033TJ180 has been designed to allow low-drop operation in a low area (the PMOS pass device has been scaled for a voltage drop of 500mV). To achieve these goals, the S3REG5033TJ180 requires a 1μF external ceramic capacitor.
- TowerJazz 0.18μm TS18 Standard Logic Process
- Only 4 Metals Used
- 3.3V Input Voltage
- 1.8V Output Voltage ±2%
- 50mA Load Current
- Die Area: 0.69mm2
- Leakage: 10nA
- Programmable Output Voltage in 80mV Step
- Power Down Mode
- The S3REG5033TJ180 uses 3.3V thick oxide devices from a standard 0.18μm logic process. The circuit can be scaled for a range of load currents and the output voltage level is programmable.
- For maximum flexibility, the user can adjust the regulated output voltage if the S3REG5033TJ180 is placed on a different chip.
- Deep N-Well is used to enhance substrate noise isolation. Its use is optional.
- The S3REG5033TJ180 is readily portable to any similar manufacturing process or can be customised for specific customer requirements.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
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Block Diagram of the High PSRR 50mA Regulator IP Core