The MIPI M-PHY IP is compliant to the MIPI® Alliance M-PHY specification and supports a wide range of advanced CMOS digital logic processes. The fully integrated hard macro M-PHY is a high-speed serial interface to the DigRF v4 and UniPro interconnect standards of the MIPI alliance. The high-quality DesignWare MIPI M-PHY IP is designed to provide mobile devices targeting 4G speeds with high data rates, low power consumption, effective power management schemes, robustness against RF interferences and low RF emission. The MIPI M-PHY IP supports the MIPI DigRF v4 standard through the use of Type-II M-PORTs, allowing for SYS-BURST LS modes together with High-Speed Gear 1 A and B modes at 1248 Gbps and 1456/1459.2 Gbps per lane respectively. In addition to the BURST-mode operation, the DesignWare MIPI M-PHY IP incorporates several power-saving states to considerably increase the power efficiency. The MIPI M-PHY IP implementing single Tx and dual Rx lanes is a fully modular architecture for use with all modes outlined in the DigRF v4 specification, including LTE 20 MHz. The single Tx and dual Rx lane configuration accommodates the DigRF v4 interface bandwidth requirements for Master baseband IC (BBIC) applications.
Expandable number of M-TX and M-RX lanes .
Support for high-speed GEAR1, GEAR2, GEAR3 A/B modes and Type-II LS mode.
Available in a wide range of advanced process technologies . Supports all modes of the MIPI DigRF v4 specification .
Optimized power consumption. Small area
0.9V + 10% digital supply operation . 1.8V + 10% analog supply operation .
Includes power optimized clock multiplication unit for high-speed and low-speed clock generation .
Optimized EMI performance through the use of slew-rate control and dithering.