Solomon codes, a class of error correction codes, are block-oriented coding schemes used in communication systems for FEC (Forward Error Correction). Information coding prior to transmission is performed against limited transmit power/bandwidth. ReedSolomon decoding architectures contribute to systems that are sensitive to transmission errors, with no data acknowledge or data retransmit. They are well suited for correcting errors that occur in bursts. Combined with a Viterbi coding scheme, ReedSolomon codes can be used to create concatenated code with increased performance.
This IP core has been designed and verified using Cadence state-of-the-art EDA tools, methodology and recommended design and verification flow.
- Implements many different ReedSolomon standards including all ITUT J.83 and CCSDS
- Interface with handshaking signals
- Multiple channel optional embodiment
- Frame lengths may vary within a valid range
- Symbol clock rate is allowed to be specified, defining a system/symbol clock rate ratio
- Internal buffering allows the blocks to be continuously fed into the core
- Block length value userconfigurable
- The number of information/check symbols transmitted userconfigurable
- Symbol width userconfigurable
- GF primitive polynomial userconfigurable
- Optional port may be configured to monitor both originally received and encoded data
- Optionally configured synchronous reset and clock enable and dedicated ports
- Optional port profile automatically adjusted against the core functional profile selected
- Core customization against the application requirements supported by parameterized, flexible IP core implementation
- Single clock synchronous design
- Technology independent HDL code
- SoC integration support
- Core configuration/customization support
- Block length value user-configurable. The number of information/check symbols transmitted user-configurable. Symbol width user-configurable. GF primitive polynomial user-configurable. Optional port may be configured to monitor both originally received and encoded data. Optionally configured synchronous reset and clock enable and dedicated ports. Optional port profile automatically adjusted against the core functional profile selected. Core customization against the application requirements supported by parameterized, flexible IP core implementation. Single clock synchronous design. Technology independent HDL code. SoC integration support. Core configuration/customization support
- Reed-Solomon encoder IP core Verilog source code.
- Reed-Solomon encoder IP core VHDL source code, if this option is selected by the customer.
- The set of configuration files
- Reed-Solomon code configuration
- IP core functional profile
- IP core boundary configuration
- CCSDS, IEEE-802.16, ATSC, DVB automatic configuration support
- The IP core test environment developed in Verilog HDL.
- Architecture specification
- Microarchitecture (RTL) specification
- TC definition document
- Testbench structure document
- SoC integration dedicated information
- Reference Reed-Solomon encode algorithm C implementation, if this option is selected by the customer.