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Full eNB-IoT Release 14 IP solution with multi-constellation GNSS support for IoT devices
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True Random Number Generator Core
The security strength of many systems and applications is dependent on the quality of random number generators. Many cryptographic operations require a source of random numbers, such as the creation of cipher keys.
The DesignWare® True Random Number Generator (TRNG) Core combines a whitening circuit with a noise source that may be used to seed a random number stream as well as provide an ongoing source of entropy. The core is therefore classified as a Non-deterministic Random Bit Generator (NRBG) using the terminology preferred by the National Institute of Standards and Technology (NIST). The noise source does not depend on process-specific circuitry and is therefore very portable across different ASIC and FPGA fabrication technologies.
The DesignWare® True Random Number Generator (TRNG) Core combines a whitening circuit with a noise source that may be used to seed a random number stream as well as provide an ongoing source of entropy. The core is therefore classified as a Non-deterministic Random Bit Generator (NRBG) using the terminology preferred by the National Institute of Standards and Technology (NIST). The noise source does not depend on process-specific circuitry and is therefore very portable across different ASIC and FPGA fabrication technologies.
Features
- Designed for compliance with FIPS 140-2 and FIPS 140-3 (draft)
- Area: 15-20K ASIC gates
- High speed operation: 50 Mbps at 200 MHz
- Configurable for ASIC and FPGA
- Redundant internal seed generators
- Lockup-free LFSR design
- Automatic and manual reseeding
- Two independent background automatic reseed modes
- Shift register compatible output stream for auxiliary uses: Differential power analysis; Timing analysis; IPsec
- Memory mapped register interface: Optional 5-wire handshake interface for host-less instantiation
Deliverables
- Verilog HDL developed in compliance with the IEEE 1364 Verilog-2005 standard
- Testbench and test vectors
- Sample synthesis script and constraints
- Sample simulation script
- Documentation and Basic Software Development Kit (SDK)
Video Demo of the True Random Number Generator Core IP Core
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