Codasip video blog series 1, part 1: Expanding RISC-V processor portfolio
The first series of Codasip video blog aims to cover embedded processor fundamentals from a practical perspective, explaining the basic features and offering valuable hints on how to get the optimal result for production. The series is focused on open standards, namely on RISC-V, the most popular open ISA (Instruction Set Architecture) today. Codasip's RISC-V processors are used to illustrate the basics and to explain how an off-the-shelf processor design can be modified to match the specific needs of its future application.
Part 1: Roddy, the Senior Marketing Director, introduces Codasip's RISC-V processor portfolio consisting of the Bk and the SweRV family, explains their difference and complementarity, and advises on what to look for when selecting a starting point to build your system-on-a-chip.
In the next parts of this video blog series, we will proceed to cover further aspects of processor design and deployment, helping you understand the impact of your choices on the final result. Subscribe to our channel to be notified of the upcoming Part 2: What is processor performance?
Posted on Tuesday Sep. 08, 2020