HMC-Xactor is a comprehensive memory VIP solution portfolio for Hybrid Memory Cube (HMC 2.0) targeting a new standard in memory performance, density, power consumption, and cost. HMC-Xactor targets SoC and memory controller designers using external HMC devices and PHY developers to ensure comprehensive verification and protocol and timing compliance. HMC-Xactor implements a complete set of models and timing and protocol checkers utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM implementation.
- HMC device model supports DUT is HMC memory controller and processes all commands, and supports command completion coalescing, randomly delayed and out of order responses (link-vault-RBC addr). Supports device chaining topologies.
- HMC Host model supports DUT as HMC device/cube and includes Power-on and initialization, automatic tag generation, supports random configuration of capability registers for more comprehensive testing, and automatic completion queue processing
- Models support flexible and unencrypted timing class for customization including random constraints for link/vault switch, DRAM access times, and refresh and scrubbing
- Supports other features including serial and parallel interfaces, bypass mode to skip power-on reset, lane polarity and reversal, independent link power state management, chaining, and automatic flow control and retry
- Inject errors at all layers through callbacks
- Random constraint sets for packet reordering at link input buffer and vault controller, and out of order, split, delayed responses
- Direct and ERI configuration register access supported (I2C and JTAG interfaces)
- Comprehensive protocol and timing checks
- Timing and functional coverage monitor for average bandwidth, read ratio, and min/max latency, coverage of commands, access sizes, and link/vault/RBC parameters
- Tracker log monitors all levels and improves debug
- HMC host and device BFMs
- User Guide