Questa Verification IP PCIe supports all PCIe speeds from Gen1 to Gen6 for providing complete verification solution for design containing PCIe interfaces. Built upon native System Verilog and UVM, QVIP for PCIe provides bus functional models (BFM) with complete functionality on latest specification for all PCIe use models. QVIP for PCIe comes with support for all kinds of packets/stimulus over the PCIe interface, ensuring extensive coverage of verification scenarios and exhaustive checking with built-in assertion checks. Architected for ease-of-use, QVIP is easy to integrate in all test benches in minimal time, quickly enabling productive verification. QVIP is integrated with all Siemens EDA functional verification tools and enables verification on all platforms, ensuring fast and complete verification closure. QVIP supports on all major simulators (Questa Sim, VCS, and Incisive) and methodologies (UVM). QVIP for PCIe enables verification of PCIe interfaces in various configurations for verifying RC, EP and Switches over PIPE and Serial interfaces. QVIP for PCIe supports the PCIe Base specification and drafts.