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SGMII e Verification Component
The SGMII e Verification Component is part of a verification environment where a frame comprised of control and data code groups are input from a test or programming application and driven onto the Serial Gigabit Media Independent Interface (SGMII). The SGMII eVC is designed to support full state machine testing for transmit, receive, synchronization and auto-negotiation. The SGMII eVC will support operation in both half and full duplex, and at interface speeds of 10, 100 and 1000 Mb/s.
Features
- SGMII compatible PHY or MAC interface
- Modular, synchronous design
- Compliant to the Cisco SGMII specification
- Standalone mode for testing without simulator or RTL.
- Integrated 8b/10b ENDECs
- Full duplex
- Compatible to Intrinsix SGMII to GMII Conversion Module
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IEEE 802.3 compliant MAC layer to PHY layer interface
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