By Cosmic Circuits
With the explosion of mobile platform devices, and the increased functionality in each of these devices, data rates between peripherals have seen exponential growth. The wide-scale adoption of 3G, LTE and upcoming 4G standards have pushed up data rates in mobile devices significantly. Cameras in mobile phones have started to support 5M pixels and above as standard. Displays have become richer with better resolution and bigger size. Indeed, many manufacturers have adapted the 3D technology to mobile phone recently. Further, solid state memory storage have increased in size and speed. These will push up the data rate demands of these peripherals.
The Application processor which processes this data and communicates with the various functions needs a high bandwidth pipe to handle the increased data throughput requirements. Serial interfaces fit well to serve these high throughput pipes. Proprietary interfaces, while serving the bandwidth requirements, complicate interoperability between the peripherals and the application processor.
Recognizing this, the MIPI alliance has been defining standards for these serial interfaces. D-PHY, which was ratified 1.5 years ago but with a near final version for 3 years, supports 1Gbps per lane. The M-PHY specification, whose 1.0 version is about to be ratified, supports about 1.25Gbps/1.5Gbps and has options to support 2.5Gbps/3Gbps and 5Gbps/6Gbps per lane.
The most successful usage of the DPHY has been in the Camera to Application Processor (CSI) and Application processor to Display (DSI) pipes. D-PHY is a source synchronous system requiring transmission of a clock along with the data. It has 2 modes of operation, a high speed mode and a low speed mode. The high speed mode used low swing differential signaling while the low speed mode uses LVCMOS level swings.
As the bandwidth requirement increases, multiple D-PHY lanes would be required which increases the system cost. This problem has been addressed by the MIPI alliance through the M-PHY. The M-PHY has been defined as an asynchronous system with the clock embedded in the data stream itself. A 3Gbps M-PHY sub-link requires only 2 signals (1 Data lane) while an equivalent D-PHY system would have required 4 times the number of signals (3 Data lanes + 1 Clock lane) resulting in lower power and cost for data transmission.. The MPHY further defines higher data rates scaling to 6Gbps for future applications.
Apart from the HS mode, the MPHY also defines 2 types of mutually exclusive Low Speed modes. Type 1 systems use the PWM mode wherein the clock is embedded in the data lanes. Data rates in the PWM mode depends on the gears supported. The default mandatory Gear is G1 with speeds ranging from 3Mbps to 9Mbps. Each additional gear supports 2X the speed range (for example G2 supports 6Mbps to 18Mbps). While gears up to G7 are defined in the specification, gears upto G5 is expected to be more widely used from a power perspective. Additionally, a low speed Gear G0 is defined which uses a slightly different signaling speed and can achieve rates down to 10Kbps.
The PWM mode can support an OMC (Optical Media Converter). OMC helps in increasing the distance between the transmitter and Receiver by converting the electrical signals to optical signals. In systems such as flip-phones, where the cable length is large or is twisted round tight corners OMC helps mitigate the signal degradation. To the MPHY system, the OMC is a transparent block which helps in keeping the modularity of the system.
The other low speed system is the SYS mode, called the Type II system. SYS mode is source synchronous in that a clock is needed to sample the data. This clock is common to both the transmitter and receiver. SYS mode signaling is relatively straight forward and hence easy to implement in systems not wishing to have the PWM mode. DigRFv4 has chosen to implement the SYS mode for its low speed mode.
Unlike the DPHY, the LP mode in MPHY uses low voltage differential signaling. This makes the driver designs relatively easy. The drivers and receivers are power optimized for the low speed mode of operation
The MPHY is a self consistent physical layer with a lot of flexibility in programming header sequences added to the payload. For example,the duration of the Prepare time which wakes the receiver and prepares it to receive the data, and the SYNC length which aids the receiver to lock in to the signal and extract the clock, are programmable over a wide range. The PHY takes the data from the controller using the SAP primitives with handshakes to ensure no data is lost.
Ubiquitous PHY layer
Given the flexibility offered by the MPHY physical layer, it is being chosen as the physical layer implementation in many applications. DigRFv4 uses the MPHY layer with SYS mode (Type II) as its LP implementation. The JEDEC defined Universal Flash Storage (UFS) specification uses UniPro v1.4 controller for its transport and lower layers. The Unipro v1.4, in turn, uses MPHY as its physical layer. The Camera Working Group is actively developing Camera Serial Interface 3, a scalable, high-bandwidth serial interface based on the UniPro protocol layer and M-PHY physical layer. It offers guaranteed data transmission and a command set for basic component initialization and configuration. The Display working group has also adopted the UniPro controller for DSI-2 and uses the MPHY for its physical layer. The Low Latency Interface uses the MPHY as its physical layer though the controller is different. The LLI is designed to be used in, as the name suggests, real time data systems where latency of the data has to be kept low. Example are modems and chip-to -chip real time data transfer ( eg video image processing ). The modularity and flexibility offered by the MPHY will see its adoption in many more applications.
Fig 1: Example usage of MIPI MPHY in a Mobile Phone
In typical usage scenarios, the MPHY will cohabitate with various cellular devices in the system. The MPHY data rate spans the cellular transmission frequencies, like the GSM, GPS and 3G. Interference between these systems have to be kept at a minimum for successful system implementation. The common mode of the output signal will have this component due to various mismatches in the chip and signal traces on the PCB. This common mode variation can impact the cellular transmission. The reverse is also true in that the common mode of the Receiver sees the interference from various sources in the mobile platform. The specification does impose a limit on the common mode variation at the output of the TX. This is designed to let even the most sensitive application, eg GPS, to work without any impact. There are 2 different rates specified, Rate A and Rate B which allows the interference from the signal strength of the MPHY to be placed at a place where it will have lower impact.
|HS Gear ||RATE A (MHz) ||RATE B (MHz)|
|G1 ||1248 ||1457.6|
|G2 ||2496 ||2915.2|
|G3 ||4992 ||5830.4|
Table 1: Data rates for the various HS Gears in Rate A and Rate B
The edge rates of the differential signals can also be programmed to reduce the spectral content of the common mode. In addition to this, the HS burst start can be dithered to spread the spectral tones around. This has to be managed by the PHY so as not to add any unreasonable constraint on the controllers.
The performance of any High Speed serial interface will be determined, amongst other things, by the jitter in the Tx and Rx sides. The jitter impacts the eye opening and sampling cleanliness directly. Jitter in the PLL and the CDR are due to intrinsic device noise as well as noise coupled from supply and ground. Jitter introduced elsewhere in the data path is mostly due to supply / ground noise. Additionally, the signal traces on the PCB are subject to system generated noises, both common-mode and differential. These are specified in the MPHY standard . The ability to tolerate more noise than specified is usually welcome from a system point of view. In systems with somewhat large distance between the Tx and Rx, ground-shift should also be taken into consideration.
The MPHY will be used, in conjunction with the controllers, in a variety of scenarios. Most of them will be in a fairly noisy environment. This could be a result of being integrated in a complex SoC with significant digital logic or in applications requiring low cost solutions, necessitating cheaper packages which tend to increase noise (pin counts and lower substrate layers in BGAs can lead to increased noise).
The ability of the M-PHY to work reliably in a noisy environment is hence very important. The M-PHY needs to reject the noise on the supply and have low intrinsic jitter to enable high speed data rates. The introduction of noise filtering LDOs in the supply chain and usage of differential architectures where ever possible helps in fighting the effects of supply noise. The M-PHY is also sufficiency guarded against noise introduced from the substrate by using suitable guard rings and isolation techniques. The Receiver input has to have the ability to reject a large common mode noise at its input and also have sufficient sensitivity to detect small eye openings.
Fig 2 : Eye Diagram at the receiver in G2B gear with receiver offsets and jitter added
Figure 2 shows the eye diagram of a G2B system , at the receiver output , with mismatches and jitter introduced by various components considered. In the Blue is the data and the red indicates the recovered clock.
Another key parameter of an IP is its testability, esp in an integrated SoC. The ability to do self-test to detect the health of the PHY is invaluable. It also obviates the need to have expensive test equipments for final test. This helps reduce the cost of the entire solution. A digital loopback test is described in the MPHY specifications itself. Additionally, the ability to load random data from the Tx and loop it through the Rx helps do BER / functional checks testing without expensive test equipments. These modes also help concurrent functional testing with the SoC tests in the final ATE.
The ability to support lower amplitudes in the TX transmitter coupled with analog loopback helps in checking the receiver sensitivity in the ATE without using expensive equipments.
Modularity of Cosmic solution
Given its anticipated wide-spread usage, the implementation of the MPHY has to be kept modular. The ability to interface with many controllers with no load on them as far as PHY layer additions is concerned should be kept in mind. Cosmic Circuits’s solution offers this modularity. The Transmitter and Receiver blocks are modularized with the common blocks like the Bandgap, PLL and common LDOs kept in a separate Common block. With this common block, it is possible to add up to 2 Tx and 2 Rx for a HS-G2 solution and up to 4 Tx and 4 Rx for a HS-G1 solution. The layouts are also done to enable connectivity by abutment. This enables rapid customization for any configuration. Of course, both the LP modes, PWM ( Type I ) along with OMC and SYS (Type 2) are supported by the Tx and Rx modules.
Each sub link ( Tx / Rx ) interfaces to the controller via the PPI interface. Support for 40, 20 or 10 bit bus widths ensures compatibility with a lot of controllers and applications.
The MPHY protocol is positioned to enter a wide array of applications. The modularity and flexible feature support will see it getting adopted by many applications in mobile phones and hopefully outside of it too. The scalability of the speeds and lanes offer sufficient customization to optimize power and cost. This will help the cost of the products to come down while keeping the end equipments feature rich.
The ability of the M-PHY to work in harsher environments than anticipated will be a requirement in actual systems. Receivers that are higher tolerance to jitter and noise, ability to work with a wider range of external components ( or even in their absence ) etc make the IP more robust and producible in volumes without impacting the SoC yield. While doing these, it is imperative to keep the power and area budgets under control.
* “MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions.”