USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
Addressing MIPI M-PHY connectivity challenges for more efficient testing
Chris Loberg, Tektronix
embedded.com (September 20, 2014)
As the industry moves to adopt the MIPI Alliance's M-PHY standard, designers are encountering some significant challenges related to oscilloscope measurements and, more specifically, probing. These challenges include strict requirements such as bus termination and input return loss, as well as the need to minimize common mode loading on the device under test (DUT) and signal fidelity requirements such as wide bandwidth, low noise, and high sensitivity.
The intent of this article is to provide information that will increase your chances of accurate and repeatable test results to ensure compliance with the standard. We will first review the requirements of the M-PHY standard relevant to oscilloscope probing, discuss the tests required in the M-PHY Physical Layer Conformance Test Suite (CTS), and provide practical examples of M-PHY probing with currently available oscilloscopes and probes.
E-mail This Article | Printer-Friendly Page |
|
Related Articles
- Understand and perform testing for MIPI M-PHY compliance
- Integrating VESA DSC and MIPI DSI in a System-on-Chip (SoC): Addressing Design Challenges and Leveraging Arasan IP Portfolio
- M-PHY benefits and challenges
- MIPI M-PHY takes center stage
- Chiplet Strategy is Key to Addressing Compute Density Challenges
New Articles
- The Rise of RISC-V and ISO 26262 Compliance
- Synopsys 3DIO Solution for Multi-Die Integration (2.5D/3D)
- SoC NoCs: Homegrown or Commercial Off-the-Shelf?
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs