Hierarchy Management for Million Plus Gate Counts

by  Barry West, AMIS

Introduction

The use of hierarchical design methods is becoming almost essential as device gate counts continue to increase well into the millions. The use of a traditional flat design process is rapidly becoming unfeasible. Although it is almost being forced upon engineers, the emergence of hierarchy management for deep sub-micron and other complex devices has numerous significant benefits for the design, the design team and the end customer.

Flat design methodology limitations

Flat design methodology works well for relatively straightforward chip designs with low gate counts. The basic design flow is broken into two linear stages: logical design and physical design. Only once the logical design is complete can the physical design be considered.

Both phases, incorporate a simple simulation feedback mechanism. A major drawback is that as more complex designs are attempted using flat methodology, these loops have to be repeated more and more before a satisfactory design is achieved.

A further disadvantage is that flat design does not lend itself easily to partitioning, either in terms of layout, placement or test. The gate quantity limitations of the various pieces of equipment used in chip design mean that partitioning is vital in larger devices, multiple FPGA to ASIC conversions and SOC applications.

Why is Hierarchy needed?

The latest system on chip (SOC) solutions and other designs that combine several chips into one device have a quantity of gates that may be in excess of five million. The project to successfully complete such designs must be planned carefully if design times and specifications are to be met. The design must be partitioned and shared amongst a team of engineers with due consideration given to individual areas of expertise, software design compiler size limitations, test equipment and completion timing targets. Good planning at this stage will result in a minimum of problems later on.

Software design compilers that are used to optimize the routing and placement of designs are typically limited to between three hundred and five hundred thousand gates. Similar restrictions also apply to design verification test benches.

A further reason to adopt hierarchy management is to ease the use of intellectual property (IP) blocks. It is far easier to insert an IP block into a hierarchical modular structure than to try and fit it into a flat design.

Timing management

Tighter timing specifications resulting from the use of fast embedded processors and complex, high gate count deep sub-micron designs have created new challenges for ASIC designers. It is likely that these will become greater as process geometries shrink further in the future.

One of the advantages of hierarchical design over flat design is that it is better able to overcome these problems and achieve successful timing closure. Companies like AMIS use synthesis tools with built in placement algorithms to give accurate timing predictions of the placed and routed design at block level. After routing, the block is characterized for boundary conditions. Higher-level timing driven layout uses timing models for blocks to achieve complete timing closure.

A hierarchical methodology which enables a bottom up design style enables different elements of the partitioned design team to share data much earlier in the design process. This greatly reduces the number of passes needed to achieve overall timing closure and also shortens the overall design time and cost for the project.

Signal integrity

With the advent of deep sub-micron designs, signal integrity problems that include crosstalk noise and crosstalk effect on delay have increased in a similar way to timing problems. The result is a massive increase in the number of nets that require consideration for parasitic effect. The smaller numbers that were present in previous larger scale designs could be dealt with manually. However, at 0.18 and 0.13 microns this is no longer workable.

The solution is a 'correct by construction' approach that is applicable to both flat and hierarchical designs. A further independent analysis and repair step validates the prevention steps and deals with any remaining problems. The methodologies for next generation designs are likely to incorporate algorithms that prevent the introduction of signal integrity problems in the first place.

Bottom-up layout

Hierarchical management uses 'bottom-up' methodology to complete the physical layout of complex ASIC or SOC applications.

Often, complete modules can be duplicated in several blocks of the design, this saves time and also cost, as the function and timing of the module only needs to be verified once, regardless of how often it is used. In some scenarios the basic structure of a module can be used in numerous blocks, but can be optimized for each specific instantiation.     Although less beneficial for time and cost, it can give better timing results.   These two concepts are known as uniquified and non-uniquified hierarchy.

Differences in clock delay or 'skew' between various blocks of the physical layout are inevitable in the initial layout of a bottom up hierarchical design. Clock tree synthesis is used to balance the skew between registers throughout the hierarchy and overcome this problem.

Once the bottom up layout has been completed a physical tool such as Apollo can   generate a net list that matches the original hierarchical structure. In order to achieve a complete match this may need to include extra block pins to account for changes made during the timing closure process. A hierarchical parasitics file is also generated during extraction of this net list. Once this stage has been completed, a variety of tools can   used for hierarchical back annotation, delay calculation, SDF generation and design checking.

Post layout verification is the final step in the process. There are many types of simulation available, and these can be selected to suit specific customer needs. Examples of typical verification processes that can be carried out are: Block level / top-level static timing analysis, block level / top level functional verification and block level simulation.

Logical and physical hierarchy

In a design, the structure of the net list hierarchy does not necessarily represent the best hierarchy to use for the layout (physical hierarchy) of the design. A truly effective flow must be able to achieve the necessary physical hierarchy whilst maintaining the logical hierarchy for the final net list.

End user benefits

Hierarchical management applied to system on chip designs has significant benefits for the customers of companies like AMIS. The ability to partition the design process means that the appropriate amount of resource can be allocated to the project to ensure that lead times are met. This can give important time-to-market benefits for the customer.

The block structure of the design coupled with the repeated use of modules wherever possible makes future modifications or de-bugs much easier to apply.  A further benefit is that the final net list will have the same structure as the original design. This makes it very recognisable and familiar to the customer.   This can be beneficial to customers for applications such as when multiple FPGA's have been combined into a single ASIC.

Meeting future design and layout requirements

The process of hierarchical management for system on chip and multiple FPGA to ASIC conversions looks set to be around for some time. Advances that will increase gate counts still further can be accommodated by further partitioning of the design into a larger quantity of blocks.

A factor that may counteract the increase in partitioning, is an increase in the number of gates that various pieces of design, placement and verification equipment can handle. Software developments may mean that in future such equipment may be able to manage one million gates or more rather than 400,000 at a time.