ESL Design Articles
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Embedded system virtualization for executable specifications and use case modeling (Feb. 01, 2010)
To reduce the time-to-market of embedded system projects, virtual hardware platforms offer a method to develop hardware-dependent software and application software before production hardware is available. However, for true system-level specification and architecture optimization, full-system virtualization is required, including abstract models of HW, behavioral models of application SW and use cases.
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Virtual testing with model-based design (Aug. 17, 2009)
Virtual testing, based on system simulation and Model-Based Design, takes the traditional "test-at-the-end" system development process and makes it more iterative. Virtual testing shortens both the design cycle and the final physical testing phase.
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Modelling Embedded Systems at Functional Untimed Application Level (Jun. 25, 2009)
We propose a structured methodology to allow flexible, accurate and fast system modelling at Functional Untimed Application Level. The methodology is built on 4 levels of abstraction, from the IP Level up to the Use-case Level, where the bottom level gives us accuracy, while the top gives us speed.
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Assisted Creation and Refinement of Transactional Level Specifications Based on IP-XACT (May. 18, 2009)
High abstraction levels, design automation and reuse are currently the three main axes to solve the productivity gap issue. This paper describes a high level platform prototype based on IP-XACT. It supports SystemC models and simulations; and also provides a set of tools for fast design generation and simple user experience.
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Advances in SoC and Processor Modeling Methodologies (Apr. 27, 2009)
Increasing complexities of the programmable components demand newer modeling methodologies. Architects need to evaluate various design constraints in a short time and also generate tools for the new architecture. Although SoC and processor modeling has been around for a long time, newer methodologies are still being put forward to overcome limitations like limited architecture modeling capabilities, slower simulation speeds, little/less validation support, issues with synthesis, etc.
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Hardware Design Requires Hardware Design Languages (Apr. 23, 2009)
While languages such as C++ can help in the creation of high-level models of hardware, Sean Dart argues that hardware engineers need specific language constructs in languages such as SystemC that allow them to express their intent in the most accurate and productive manner.
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SOC Virtual Prototyping: An Approach towards fast System-On-Chip Solution (Apr. 13, 2009)
In this paper, we discuss the Transaction Level Model which is being developed to act as Virtual Prototype in digital image processors designed to fit into mobile applications. As part of our developments new methodology TLMdevice is also defined which provides way to connect TLM simulations to communicate with not only virtual host devices such as Graphical window, Keyboards but also real host devices like UART, Display and Sensors, so that data can be easily sent and received to/from during TLM simulation run
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A SystemC-Based RTOS Model for Multiprocessor Systems-on-Chips (Mar. 19, 2009)
With the increasing complexity of embedded systems and the capacity of modern silicon technology, there is a trend toward heterogeneous architectures consisting of several programmable as well as dedicated processors, implemented on a single chip, known as systems-on-chips (SoCs).
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A SystemC/TLM based methodology for IP development and FPGA prototyping (Nov. 03, 2008)
With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally becoming insufficient to fit into this new role. These factors are driving designers to explore new methodologies for early verification of complex IPs (HW as well as SW) as well as complete system.
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Virtual prototypes speed wireless development (Oct. 27, 2008)
Wireless engineers are leveraging virtual prototypes of their system-on-chip designs to improve product quality and speed time to market. A virtual prototype can be an indispensable tool for performing early architectural analysis for throughput and power tradeoffs.
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Borrowing from software to use SystemVerilog test bench debug & analysis (Oct. 23, 2008)
Shrinking silicon geometries enable larger SoC-type designs in terms of raw gate size, and many of today's applications take advantage of this trend. An important point that is often missed is the accompanying growth in verification complexity.
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ESL handoff: closer than you think (Jul. 08, 2008)
Any viable design methodology requires tight links to implementation, and to meet this need a new generation of High-Level Synthesis tools is emerging, based on SystemC.
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Leveraging OCP for Cache Coherent Traffic Within an Embedded Multi-core Cluster (Jul. 07, 2008)
Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters.
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Generic Driver Model using hardware abstraction and standard APIs (Jun. 30, 2008)
This paper describes a unique approach for developing drivers using hardware abstraction and standard APIs for hardware and software interfaces.
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Leveraging Virtual Platforms for Embedded Software Validation: Part 2 (Jun. 26, 2008)
The article will discuss how to effectively use interface and abstraction techniques, modeling tools, debugging techniques, and profiling to characterize and validate architectures and embedded software.
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Adapter Based Distributed Simulation of Multiprocessor SoCs Using SystemC (Jun. 02, 2008)
An ever increasing demand for execution speed and communication bandwidth has made the multi-processor SoCs a common design trend in today’s computation and communication architectures.
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ESL Methods for Optimizing a Multi-media Phone Chip (May. 27, 2008)
This article describes experiences with the adoption of ESL for optimizing the architecture of a multi-media cellular phone platform.
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Debugging a Shared Memory Problem in a multi-core design with virtual hardware (May. 22, 2008)
With multicore systems becoming the norm, software developers have found the debugging of such systems, using a physical hardware development board, to be very challenging, particularly when it comes to the integration of applications sharing data across multiple cores.
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Rapid Creation of Application Models from Bandwidth Aware Core Graphs (May. 19, 2008)
We present a methodology that allows the rapid creation of application models from bandwidth aware core graphs that are available in the literature for a wide range of applications and we discuss their applicability to the rapid exploration of multiple Networks on Chip (NoCs) layout organizations.
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How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1 (May. 01, 2008)
Using advanced HDLs like SystemVerilog, current hardware modeling styles can be enhanced both in terms of abstraction levels and overall efficiency.
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SystemC: Key modeling concepts besides TLM to boost your simulation performance (Mar. 24, 2008)
Virtualization of SoC, ECUs and other electronic systems is used to explore (micro-)architectures at system level as well as to develop and verify software early in the design cycle.
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Electronic system-level approach shortens SoC design (Feb. 14, 2008)
The main reason for designing systems-on-chip at the electronic system level is to reduce time-to-market, development cost and power consumption.
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Hardware design using ESL (Feb. 11, 2008)
To build increasingly sophisticated chips, engineers must be freed from low-level details and limiting methodologies. ESL design flows raise the level of abstraction from the register transfer level (RTL) to the system level.
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Fast virtual platforms open up multicore software development (Feb. 11, 2008)
Virtual platforms aid the short-term market takeoff of multicore architectures as well as their long-term acceptance and success.
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Accelerating High-Level SysML and SystemC SoC Designs (Feb. 04, 2008)
The goal of this research is to analyze the mapping between SysML and SystemC, propose and suggest the SystemC modeling techniques that should result in modeling both the structure and behavioral SysML diagram to produce a single executable that represents the system behavior. A prototype for a translation tool, a SysML model compiler, has been implemented using a UML editing tool that supports SysML.
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Putting the system in electronic system design (Feb. 04, 2008)
Increasingly complex systems and technologies like multicore processors and FPGAs have rendered old design methodologies obsolete. New approaches are needed: system-level abstractions that handle complexity, and tools that automate the costly, time-consuming steps between concept and implementation.
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A Chip IP Integrator for System Level Design (Jan. 14, 2008)
This paper describes a new approach for chip design and system-level integration. A hierarchical RTL context-preserving insertion and connectivity methodology has been further implemented in EDA tool – chip IP integrator. This paper shares the approach, methodology and the results on a real-life system comprising several RTL design blocks in Verilog each having around a quarter of million instances as well as on an ARM 4 CPU test chip design.
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Viewpoint: RTL-ers should move to ESL (Oct. 22, 2007)
Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed.
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How effective use of ESL tools can increase your HW/SW system design productivity (Oct. 05, 2007)
The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers.
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Design of a C library for the implementation of 3D graphics applications on a SoC (Sep. 17, 2007)
In this paper a new approach to the implementation of 3D graphics applications on a SoC architecture is described. This approach is meant to be particularly flexible, in order to be used in different kinds of systems: it is based on the realization of software libraries, that are developed using the C programming language.