Digital Blocks Delivers the DB1800 NTSC / PAL / SECAM Video Sync Separator IP Core
GLEN ROCK, New Jersey, August 16, 2006 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for embedded processor and video system designers, today announces the DB1800 NTSC/PAL/SECAM Video Sync Separator IP Core. The DB1800 is an all digital design for standard definition NTSC/PAL/SECAM VLSI video decoder applications. The DB1800 accepts a NTSC/PAL/SECAM composite video signal, auto-detects the standard, and outputs the horizontal sync, vertical sync, chroma burst blanking, and field 1 or 2 (odd or even) detection. In addition, the DB1800 provides a display enable signal, which indicates which video lines and which segment of a video line contain active video.
Price and Availability
The DB1800 is available immediately in synthesizable Verilog, along with synthesis scripts, a simulation test suite, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1-208-379-1012; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface.
- Digital Blocks Announces 2nd Gen Audio/Video & Data Hardware Protocol Stacks Supporting MPEG2 Transport Stream (TS), RTP, and UDP/IP Protocols
- Digital Blocks Expands Video Signal & Image Processing IP Core Family
- Actel's CorefIR v4.0 Delivers Configurable Digital Filter Generation for Rtax-DSP with On-Chip Math Blocks
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |