32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Renesas Achieves 3X Reduction in Chip-Finishing Turnaround Time Using Cadence QuickView Signoff Data Analysis Environment
SAN JOSE, Calif., Jul 24, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Renesas Electronics Corporation utilized the Cadence® QuickView Signoff Data Analysis Environment to achieve a 3X improvement in chip-finishing turnaround time over its previous solution. As a result of this productivity gain, Renesas has standardized on the Cadence® QuickView Signoff Data Analysis Environment to maximize tapeout productivity for all technology nodes.
The QuickView Signoff Data Analysis Environment is a high-performance, high-capacity data-analysis tool that enables viewing and superimposing of design data in any of its intermediate conditions throughout the chip-finishing process. The QuickView Signoff Data Analysis Environment is also compatible with third-party IC implementation flows and can read file formats used by third-party verification tools. The solution’s comprehensive database operations—intelligent overlay, graphical XOR capabilities, synchronized multi-windows, net tracing, LEF/DEF support, merging/converting data, and cross-section views—make graphical comparisons of data easy by providing an additional element of decision support to tapeout engineers.
“After full-chip verification, opening the database for chip finishing can take hours, and because there are several iterations at this stage, any productivity loss has a large impact on time-sensitive project schedules and deadlines,” said Tatsuji Kagatani, department manager, Design Automation Department System Integration Business Division, Renesas Electronics Corporation. “We selected the QuickView Signoff Data Analysis Environment after a stringent evaluation, wherein Cadence delivered the best performance and capabilities. This enabled our design teams to improve their productivity and reduce iterations at tapeout.”
For more information on the QuickView Signoff Data-Analysis Environment, visit www.cadence.com/news/quickview.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.
|
Cadence Hot IP
Related News
- New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time
- Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time
- Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis
- Renesas Adopts Cadence Interconnect Workbench to Accelerate Performance Analysis and Verification of On-Chip Interconnect
- Accusonus Achieves 60 Percent Reduction in Computational Cost of Speech Enhancement Software for Cadence Tensilica HiFi DSPs
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |