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Sram architecture for cost sensitive devices at 55 lp up to 10 denser than traditional memory compiler IP Listing

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Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k

Single Port SRAM compiler - TSMC 55 nm LP - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k

1
Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k

Metal programmable ROM compiler - TSMC 152 nm LP - Non volatile memory optimized for low power and high density - compiler range up to 1024 k

2
Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k

Foundry sponsored - Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - compiler range up to 640 k

3
Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - compiler range up to 640 k

Single Port SRAM compiler - TSMC 90 nm LPeF - Memory optimized for high density and Low power - Dual voltage - compiler range up to 640 k

4
Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k

Foundry Sponsored - Single Port SRAM compiler - TSMC 85 nm UP - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k

5
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k

Foundry sponsored - Single Port Register File compiler - TSMC 90 nm uLL - high density - Dual Voltage - compiler range up to 40 k

6
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits

Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits

7

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Sram architecture for cost sensitive devices at 55 lp up to 10 denser than traditional memory compiler IP Listing

Single Port SRAM compiler - Memory optimized for high density and low power - Deep N Well supported - compiler range up to 320 k

Metal programmable ROM compiler - Memory optimized for low power and high density - compiler range up to 1024 k

Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 640 k

Single Port SRAM compiler - Memory optimized for high density and low power - Dual voltage - compiler range up to 640 k

Single Port SRAM compiler - Memory optimized for ultra high density and high speed - Dual Voltage - compiler range up to 640 k

Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - compiler range up to 40 k

Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits

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