English
| |
-
Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus, Delivering Best-in-class Productivity and Quality of Results (Friday Jul. 23, 2021)
Cadence today announced the delivery of the Cadence® Cerebrus™ Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals.
-
Samsung Foundry and Synopsys Collaborate to Accelerate Time to ISO 26262 Compliance for Automotive SoCs (Monday Jul. 19, 2021)
Synopsys today announced that Samsung Foundry collaborated with Synopsys on its VC Functional Safety Manager solution. VC Functional Safety Manager (VC FSM) provides the necessary automation for the functional safety Failure Mode Effects Analysis (FMEA) and Failure Modes Effects Diagnostic Analysis (FMEDA) for automotive SoCs.
-
Cadence and UMC Collaborate on 22ULP/ULL Reference Flow Certification for Advanced Consumer, 5G and Automotive Designs (Tuesday Jul. 13, 2021)
Cadence and UMC today announced that the Cadence digital full flow has been optimized and certified for the UMC 22ULP/ULL process technologies to accelerate consumer, 5G and automotive application design.
-
IQ-Analog Adopts Diakopto's ParagonX Platform for Next-Generation 5G Wireless Communications ICs (Tuesday Jul. 13, 2021)
Diakopto announced today that IQ-Analog, a leading provider of wideband transceivers for 5G wireless systems, has selected ParagonX™ to accelerate the analysis, debugging and optimization of their next-generation integrated circuits (ICs).
-
Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market (Wednesday Jun. 30, 2021)
Imperas simulation technology and RISC-V reference models now available pre-integrated within Valtrix STING for advanced RISC-V Processor Verification
-
AnalogX Accelerates Time-to-Market with Diakopto's ParagonX Debugging Platform and Methodology (Wednesday Jun. 30, 2021)
Diakopto announced today that AnalogX has adopted ParagonXTM to dramatically speed up the development of their industry-leading AXLinkIO technology for chip-to-chip and die-to-die interconnects in process technologies ranging from 22nm to 6nm.
-
Silicon Creations Selects Diakopto's ParagonX IC Debugging Platform (Wednesday Jun. 30, 2021)
Diakopto announced today that Silicon Creations® has selected ParagonXTM to improve the design quality, productivity, and time-to-market for their industry-leading portfolio of analog and mixed-signal intellectual property (IP).
-
SiFive Collaborates with Imperas on Models of SiFive's RISC-V Core IP Portfolio (Tuesday Jun. 29, 2021)
Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that SiFive, Inc., the industry leader in RISC-V processors and silicon solutions, has qualified the Imperas models for the full range of the SiFive processor Core IP Portfolio.
-
Synopsys Strategic Partnership with Samsung Foundry Accelerates Access to Transformative 3nm GAA Technology (Monday Jun. 28, 2021)
ynopsys, Inc. (Nasdaq: SNPS) today announced that the Synopsys Fusion Design Platform™ has enabled Samsung Foundry to achieve first-pass silicon success for an advanced, high-performance and multi-subsystem system-on-chip (SoC), validating the extended power, performance and area (PPA) benefits of its next-generation, 3-nanometer (nm) gate-all-around (GAA) process technology.
-
AMIQ EDA Updates UVM Rule Checks for Latest Release of the Universal Verification Methodology Standard (Monday Jun. 28, 2021)
AMIQ EDA today announced that it has expanded the rules checked by its Verissimo SystemVerilog Testbench Linter to match the latest release (IEEE 1800.2-2020) of the Universal Verification Methodology (UVM) standard.
-
Synopsys PrimeShield Selected by Samsung Electronics to Maximize Energy Efficiency and Performance for Next-Generation Process Node Designs (Thursday Jun. 24, 2021)
Synopsys today announced its PrimeShield™ design robustness solution has been deployed by Samsung's System LSI Business on its advanced process technologies for next-generation designs spanning mobile, 5G and automotive applications.
-
Alphawave IP Adopts Diakopto's ParagonX EDA Platform and Methodology (Tuesday Jun. 22, 2021)
Diakopto announced today that Alphawave IP (AWE.L) has selected the ParagonXTM EDA software platform and methodology to help accelerate time-to-market and enhance the robustness for their market-leading high-speed connectivity solutions.
-
Diakopto Unleashes Breakthrough ParagonX EDA Tool, Platform and Methodology to Dramatically Accelerate IC Design Debugging and Optimization (Tuesday Jun. 22, 2021)
Diakopto today announced a new EDA software platform, tool and methodology developed from the ground up to address the increasing impact of integrated circuit (IC) layout parasitics on design performance, precision, power, robustness, and reliability.
-
Advantest Developing Innovative Methodologies for High-Speed Scan and Software-Based Functional Testing (Thursday Jun. 17, 2021)
Advantest Corporation is pilot testing a next-generation solution for performing both high-speed scan testing and software-driven functional device testing on the V93000 platform by leveraging the existing high-speed serial I/O interfaces on advanced integrated circuits (ICs).
-
CEA-Leti Collaborates with Siemens to Launch Process Design Kit that Supports Multiple Technologies, Simplifies Creation of Optical Circuits (Thursday Jun. 17, 2021)
CEA-Leti, a research institute at CEA, today announced that it has collaborated with Siemens Digital Industries Software to offer an updated process design kit (PDK) that enables photonic designers to select multiple methodologies, including layout centric, schematic driven and layout automation and provides access to CEA-Leti’s 300mm photonics multi-project wafers (MPW).
-
Thalia Design Automation partners with Sofics to enhance offering for analog circuit and IP reuse (Wednesday Jun. 16, 2021)
Thalia Design Automation Ltd., provider of analog and mixed-signal circuit IP reuse platform, today announced a new partnership with Sofics, a leading provider of analog I/Os, specialty digital I/Os and ESD protection.
-
Sequans Communications Adopts Cadence RF Solution to Develop Next-Generation 5G IoT Platform (Friday Jun. 11, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that Sequans Communications S.A., a leader in 4G and 5G IoT solutions, has successfully adopted the Cadence® Virtuoso® RF Solution, including the Cadence Spectre® X RF Simulator and Cadence EMX® Planar 3D Solver, for high-frequency RF harmonic balance and electromagnetic (EM) analysis and signoff, to develop its next-generation 5G IoT platform.
-
New Cadence Allegro X Design Platform Revolutionizes System Design (Wednesday Jun. 09, 2021)
Allegro X Platform Offers Unparalleled Integration and Technology Across Multiple Engineering Domains, Delivering Up to 4X Productivity Improvements over Traditional Design Tools
-
EdgeCortix Collaborates with Cadence to Accelerate AI Chip Design (Thursday Jun. 03, 2021)
Cadence today announced that EdgeCortix has deployed multiple Cadence® verification and digital tools to accelerate the design and verification of its edge AI chips.
-
Aldec Launches HES-DVM Proto "Cloud Edition" - Giving Engineers Easier Access to FPGA-based ASIC & SoC Prototyping (Wednesday Jun. 02, 2021)
Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and has a focus on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.
-
Siemens announces EDA milestones and tool certifications for TSMC's latest process technologies (Tuesday Jun. 01, 2021)
Now certified for TSMC’s N3 and N4 processes, Siemens’ Analog FastSPICE platform provides leading-edge verification for nanometer analog, radio frequency (RF), mixed-signal, memory, and custom digital circuits.
-
Cadence Collaborates with TSMC to Accelerate Mobile, AI and Hyperscale Computing Application Development on N3 and N4 Processes (Monday May. 31, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is expanding its collaboration with TSMC to accelerate mobile, AI and hyperscale computing application design using the integrated Cadence® digital flow and custom/analog tool suite on TSMC’s N3 and N4 process technologies.
-
Mirabilis Design and E-Elements Technology team up to provide concept-to-implementation design flow for AI applications (Thursday May. 27, 2021)
Mirabilis Design, leader in system simulation, joins forces with E-Elements, a leading service provider in system design, to create a breakthrough design solution that drastically reduces the turnaround time of AI software development for the medical, robotics, and autonomous driving industries.
-
Cadence Unleashes Clarity 3D Solver on the Cloud for Straightforward, Secure and Scalable Electromagnetic Analysis of Complex Systems on AWS (Thursday May. 27, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a straightforward, secure and cost-effective approach to gaining access to compute resources in the cloud when executing 3D electromagnetic (EM) simulations with Cadence® Clarity™ 3D Solver Cloud.
-
Synopsys Digital and Custom Design Platforms Certified for TSMC's Latest 3nm Process Technology (Wednesday May. 26, 2021)
Synopsys today announced that TSMC has certified Synopsys' digital and custom design solutions based on TSMC's latest design-rule manual (DRM) and process design kits for its advanced 3-nanometer (nm) process technology.
-
Siemens expands Simcenter with AI-driven generative engineering for systems architectures (Wednesday May. 26, 2021)
Siemens Digital Industries Software announces the release of Simcenter™ Studio software, a web application dedicated to discovering better system architectures, faster.
-
Cadence Collaboration with Arm Enables Customers to Successfully Tape out Next-Generation Arm Mobile Designs (Wednesday May. 26, 2021)
Cadence today announced that through a collaboration with Arm, customers have successfully taped out mobile SoCs using Cadence® tools and the next-generation Arm® mobile solution, which includes the Arm Cortex®-X2, Cortex-A710, and Cortex-A510 CPUs, Mali™-G710 GPU and the DynamIQ Shared Unit-110.
-
Synopsys Enables First-Pass Silicon Success for Early Adopters of Next-Generation Armv9 Architecture-based SoCs (Tuesday May. 25, 2021)
Synopsys today announced multiple SoC tape-outs at early adopters of the next-generation Arm® Cortex®-X2, Cortex-A710, and Cortex-A510 CPUs based on Armv9, Arm Mali™-G710 GPUs and Arm DynamIQ Shared Unit-110 were achieved using Synopsys' portfolio of industry-leading solutions.
-
JVCKENWOOD Deploys Cadence Spectre FX Simulator and Comprehensive Design Flows to Improve Productivity (Monday May. 24, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced JVCKENWOOD has adopted the new Spectre® FX Simulator and multiple Cadence® custom, analog, digital and verification solutions to accelerate IC development of its consumer electronics applications while minimizing overall design risk.
-
Cadence Introduces the Spectre FX FastSPICE Simulator Delivering up to 3X Performance Gains with Superior Accuracy (Monday May. 24, 2021)
Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the new Cadence® Spectre® FX Simulator, a next-generation FastSPICE circuit simulator that enables the efficient verification of memory and large-scale system-on-chip (SoC) designs.