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Avery Design Systems Announces SimXACT 5.0 for Improved X-Verification (Monday Feb. 26, 2018)
Avery Design Systems Inc. today announced availability of release 5.0 of its patented SimXACT analysis solutions including major new features for analyzing and automatically eliminating X bugs in gate-level design simulation.
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Metrics Partners with Avery to Expand Cloud Verification with Robust VIP Portfolio (Monday Feb. 26, 2018)
Metrics Technologies and Avery Design Systems today announced the results of their collaboration to enable Avery’s Verification IP to run on Metrics Cloud Simulator & Verification Manager. The combined pay-by-minute SaaS Solution dramatically improves both resource utilization and engineering productivity.
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QuickLogic Announces Partnership with Aldec for eFPGA Simulation Flow (Tuesday Feb. 20, 2018)
QuickLogic announced that it has partnered with Aldec, a leading design verification EDA company, to provide seamless simulation support for its embedded FPGA (eFPGA) technology.
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OneSpin Announces Immediate Availability of OneSpin 360 EC-FPGA Tool Qualification Kit Certified for ISO 26262, IEC 61508, EN 50128 (Thursday Feb. 15, 2018)
OneSpin® Solutions announced immediate availability of its OneSpin 360 ECFPGA ™ Tool Qualification Kit certified by internationally-recognized testing body TÜV SÜD.
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Silicon Library Adopts Averant's Solidify Automated Checks Using CDC Inc. EDA Cloud Services (Thursday Feb. 15, 2018)
Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits and CDC Inc., a leading provider of EDA cloud solutions today announced the adoption of Averant's automated checks by Silicon Library Inc. in their verification flow.
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Defacto Technologies Announces Synapse Design in collaboration with a major semiconductor company Reduces Simulation Time by 5X When using Defacto's RTL Design Solutions (Monday Feb. 12, 2018)
Defacto Technologies today announced that Synapse Design has tested STAR in collaboration with a major US based semiconductor company in the GPU market. Synapse Design used the RTL design restructuring capabilities of the Defacto’s STAR platform to generate clean and ready for synthesis RTL code.
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Maxim Selects Methodics as IP Lifecyle Management Platform to Enable Enterprise IP-Centric Design Approach Across Global Design Network (Tuesday Feb. 06, 2018)
Methodics Inc, the leader in IP lifecycle management, today announced that Maxim Integrated Products, Inc. (NASDAQ: MXIM) has selected its Percipient platform for Maxim’s worldwide chip design operations.
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Metrics Announces Pay-by-Minute Cloud Simulator & Verification Manager (Thursday Feb. 01, 2018)
Metrics Technologies, Inc. today announced its flagship product, the Metrics Cloud Simulator & Verification Manager -- the electronic design automation industry’s first true cloud software solution.
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Synopsys DFTMAX LogicBIST Deployed by Renesas for In-System Automotive Test (Tuesday Jan. 23, 2018)
Synopsys today announced that Renesas Electronics has deployed Synopsys' DFTMAX™ LogicBIST solution on a mixed-signal, large scale integration (LSI) design to meet automotive safety integrity levels required by system integrators.
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Codasip Announces Studio 7, Design and Productivity Tools for Rapid Generation of RISC-V Processors (Tuesday Jan. 23, 2018)
Codasip today announced that it has launched the 7th generation of its Studio, the unique IP-design and customization software that allows for fast configuration and optimization of RISCV processors, customer-proprietary processor architectures, and their accompanying software development toolchains.
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Synopsys and Helic Deliver Unified Electromagnetic-Aware Analog and RF Custom Design Flow (Thursday Dec. 14, 2017)
Synopsys and Helic today announced that the companies have collaborated to integrate Helic's VeloceRF™ RF device synthesis, RaptorX™ EM modeling and Exalto® EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform.
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QuickLogic Collaborates with Mentor to Provide Seamless Design Environment for eFPGA Technology (Thursday Dec. 14, 2017)
QuickLogic announced that it has collaborated with Mentor®, a Siemens business, to provide a seamless design and development environment for its embedded FPGA (eFPGA) technology
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Catena selects Thalia-DA to facilitate analog IP re-use (Wednesday Dec. 13, 2017)
Thalia Design Automation today announced that is has been selected by Catena, a leader in radio frequency (RF) communication intellectual property (IP) for connectivity, to support a range of projects that will enhance Catena’s analog IP reuse strategy, as the company seeks to diversify its portfolio of products to better serve system-on-chip (SoC) designers targeting mobile, Internet-of-things (IoT) and RF connectivity markets.
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iC-Haus Selects Synopsys' IC Validator and StarRC for Signoff (Wednesday Dec. 13, 2017)
Synopsys, Inc. (Nasdaq: SNPS) and iC-Haus GmbH, a leader in application-specific ICs (ASICs) for industrial, automotive and medical technology, today announced that iC-Haus has adopted Synopsys' IC Validator and StarRC™ products for design signoff.
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Averant's Solidify 6.5 Significantly Improves Combinational and Sequential Equivalency Checking and Clock Domain Crossing Checks (Tuesday Dec. 12, 2017)
Averant Inc., the First In Formal™ leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.5.
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Synopsys and CEA Announce Partnership to Develop Emulation Solutions for Automotive Applications (Monday Nov. 13, 2017)
Synopsys and the French Alternative Energies and Atomic Energy Commission (CEA), a key player in technology research, today announced their new partnership based on Synopsys ZeBu® Server-3 emulation solution for advancing their initiatives in automotive SoC and system design.
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Cadence Joules RTL Power Solution Enables Socionext to Accelerate Low-Power HEVC 4K/60p Video Codec Chip Development (Thursday Nov. 02, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Socionext Inc. used the Cadence® Joules™ RTL Power Solution to develop a low power high-efficiency video coding (HEVC) 4K/60p chip.
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DecaWave Deploys Synopsys TetraMAX II ATPG on Latest Automotive Design to Lower Test Time 50 Percent and Speed Runtime by 10x (Tuesday Oct. 31, 2017)
Synopsys today announced that DecaWave deployed TetraMAX® II automatic test pattern generation (ATPG) to significantly reduce runtime from nine hours to thirty minutes and reduce the number of patterns by 50 percent compared to their previous test pattern generation solution for an automotive ultra-wide band transceiver IC.
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Synopsys Introduces Complete Functional Safety Test Solution to Accelerate ISO 26262 Compliance for Automotive SoCs (Monday Oct. 30, 2017)
Synopsys today introduced a validated built-in-self-test (BIST) and repair IP solution to enable designers to achieve the most stringent levels of functional safety for automotive system-on-chips (SoCs).
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Synopsys Test Platform Tools Certified for the Most Stringent Level of Automotive Safety Measures Defined by the ISO 26262 Standard (Monday Oct. 30, 2017)
Synopsys today announced that its test platform tools for high-quality manufacturing test are completely certified for the ISO 26262 automotive functional safety standard.
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Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers (Tuesday Oct. 24, 2017)
Cadence and Arm today announced early access to the Cadence® Xcelium™ Parallel Logic Simulation on Arm®-based servers, providing a first-of-its-kind low-power, high-performance simulation solution for the electronics industry.
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SiFive Selects Synopsys Verification Continuum Platform for Advanced RISC-V Processor Designs (Monday Oct. 23, 2017)
Synopsys today announced that SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has selected the Synopsys Verification Continuum™ platform as its verification solution. SiFive has deployed the Verification Continuum platform for simulation, verification IP, debug, static verification and formal coverage closure.
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Accellera Systems Initiative advances the SystemC ecosystem with a new core language library (Monday Oct. 16, 2017)
Accellera Systems Initiative announces a new library release for the SystemC core language (SystemC 2.3.2, including TLM 2.0.4). Ratified as IEEE Std. 1666-2011 "Standard SystemC Language Reference Manual," SystemC is a high-level language used in the design and development of electronic and embedded systems.
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Cadence Announces Digital and Signoff Flow Support for Body-Bias Interpolation for GLOBALFOUNDRIES 22FDX Process Technology (Friday Oct. 13, 2017)
Cadence today announced that its digital and signoff flow, from synthesis to timing and power analysis, supports body-bias interpolation for the GLOBALFOUNDRIES 22FDX™ process technology.
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Cadence Achieves TUV SUD's First Comprehensive "Fit for Purpose - TCL1" Certification in Support of Automotive ISO 26262 Standard (Wednesday Oct. 11, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has achieved the industry’s first comprehensive “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification from TÜV SÜD, enabling automotive semiconductor manufacturers, OEMs and component suppliers to meet stringent ISO 26262 automotive safety requirements.
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Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator (Tuesday Oct. 10, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Teradyne Inc. has standardized its simulation tasks using the Xcelium™ Parallel Logic Simulator to accelerate ASIC development for delivery of its automation equipment for test and industrial applications.
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Cadence Genus Synthesis Solution Enables Fuji Xerox to Improve Multi-Functional Printer SoCs Design Development (Monday Oct. 02, 2017)
Cadence today announced that Fuji Xerox Co., Ltd. used the Cadence® Genus™ Synthesis Solution to improve the development of its multi-functional printer SoCs.
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Samsung Certifies Synopsys Design Platform for 28nm FD-SOI Process Technology (Monday Sep. 25, 2017)
Synopsys today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry's 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys' Lynx Design System, containing scripts, design methodologies and best practices is now available.
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Cadence DFM Signoff Solutions Achieve Qualification for Samsung 28nm FD-SOI/14nm/10nm Process Technologies (Monday Sep. 25, 2017)
Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its set of Design for Manufacturing (DFM) tools are now qualified on Samsung Electronics’ 28nm FD-SOI/14nm/10nm process technologies.
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Mentor Precision Synthesis announces support for the eFPGA fabric in Silicon Mobility's OLEA automotive IC (Thursday Sep. 21, 2017)
Mentor, a Siemens business, today announced the Precision® Synthesis product support for Silicon Mobility’s OLEA® Field-Programmable Control Unit (FPCU) – a flexible electronic circuit tailored specifically for the automotive market and specialized in real-time processing and control.