Bluetooth Dual Mode v5.4 / IEEE 15.4 PHY/RF IP in TSMC22nm ULP
1603 Results (241 - 280) |
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Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
Oct. 01, 2018 - Cadence today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing (HPC) designs. -
BrainChip Announces the Akida Architecture, a Neuromorphic System-on-Chip
Sep. 10, 2018 - BrainChip, the leading neuromorphic computing company, today establishes itself as the first company to bring a production spiking neural network architecture – the Akida Neuromorphic System-on-Chip (NSoC) – to market. -
Synopsys Delivers 10X Performance in Formal Property Verification with Breakthrough Machine Learning Technology
Aug. 27, 2018 - Synopsys today announced a state-of-the-art artificial intelligence (AI) enabled formal verification app, Regression Mode Accelerator, as part of the Synopsys VC Formal® solution. -
Antmicro and SiFive join forces to propose complete RISC-V offering
Aug. 14, 2018 - Antmicro, a software-driven technology vendor for edge AI and cyber-physical systems, and SiFive, the first fabless semiconductor company to offer customized silicon based on the free and open RISC-V Instruction Set Architecture, are announcing a milestone partnership to bring forth a complete offering ... -
Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design
Aug. 14, 2018 - By combining the Palladium Z1 emulation platform with Cadence Xcelium™ Parallel Logic Simulation, GUC engineers were able to apply more complex SoC verification test scenarios with full debug visibility, accelerating verification by up to 795 times. -
Thalia-DA and Catena confirm successful tape-outs of first analog IP re-use projects
Jul. 31, 2018 - Thalia Design Automation and Catena, a leader in radio frequency (RF) communication intellectual property (IP) for connectivity, today announced successful completion of their first jointly delivered analog IP reuse projects. -
BrainChip Unveils the Akida Development Environment
Jul. 25, 2018 - The Akida Development Environment is a machine learning framework for the creation, training, and testing of spiking neural networks (SNNs), supporting the development of systems for edge and enterprise products on the Company’s Akida Neuromorphic System-on-Chip (NSoC). -
Dolphin Integration presents its know-how in EDA for safe Power Regulation Networks implementation at ENIAC's THINGS2DO E.U. project final review
Jun. 18, 2018 - On June 13-14th, 2018, Dolphin Integration, partner of the ENIAC’s THINGS2DO European project, showcased its achievements with PowerStudio, its cutting-edge EDA tool for safe Power Regulation Networks implementation. -
Synopsys Fusion Technology Enables Lower Power, Smaller Area, and Higher Performance on Samsung Foundry 7LPP Process with EUV
Jun. 14, 2018 - Synopsys, Inc. (Nasdaq: SNPS) today announced that Samsung Foundry has certified the Synopsys Design Platform with Fusion Technology for 7-nanometer (nm) Low Power Plus (LPP) process with Extreme Ultraviolet (EUV) lithography technology. -
Sonics Partners With Synkom To Incorporate NoC and EPU IP Into Its Leading Semiconductor Design Services For Japan Customers
Jun. 06, 2018 - Sonics announced a partnership with Synkom, a leading electronic design services firm in Japan, that incorporates NoC and Energy Processing Unit (EPU) IP into Synkom’s design flow for companies creating complex chips using Synkom’s services. -
Synopsys Design Platform Certified for Samsung 8LPP Process Technology
May. 23, 2018 - Synopsys today announced that Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, has certified the Synopsys Design Platform for Samsung Foundry's 8-nanometer (nm) LPP (Low Power Plus) process. -
Cadence Supports New TSMC WoW Advanced Packaging Technology
May. 01, 2018 - Cadence today announced that its full suite of Cadence® digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology. -
Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
May. 01, 2018 - Cadence today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. -
Synopsys and Arm Extend Collaboration to Improve Power, Performance, and Time to Results for Arm's Latest IP and Synopsys Tools
Apr. 16, 2018 - Arm and Synopsys, Inc. (Nasdaq: SNPS) have extended their collaboration and signed a multi-year subscription agreement expanding Synopsys' access to a broad range of Arm intellectual property (IP) to enable optimization of Synopsys tools and methodologies for Arm-based system-on-chips (SoCs). -
Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
Apr. 11, 2018 - Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced major enhancements to its Cadence® Virtuoso® custom IC design platform that improve electronic system and IC design productivity. -
Silvaco Completes Acquisition of NanGate
Mar. 06, 2018 - Silvaco today announced that it has acquired NanGate, a leader in Electronic Design Automation (EDA) software, that offers tools and services for creation, optimization, characterization and validation of physical library IP. -
CEVA and Nokia Collaborate for 4.9G and 5G Technologies
Mar. 01, 2018 - CEVA today announced that it is supporting Nokia in the development of its ReefShark baseband System-on-Chips (SoCs), set to be deployed for 4.9G and 5G wireless infrastructure. -
Sonics Partners With Inomize To Enable Automotive Chip Design For ISO 26262 Standard
Feb. 27, 2018 - Sonics announced a partnership with Inomize (Netanya, Israel) that enables chip designs to comply with the ISO 26262 automotive functional safety standard using Sonics’ NoCs with Inomize’s ASIC design platforms and services. -
Magillem Partners with Imperas
Feb. 26, 2018 - Together, Magillem and Imperas provide a unique virtual prototyping solution set, fully based on the IEEE standards IP-XACT and SystemC. -
Siemens continues to invest in IC industry with planned acquisition of Sarokal Test Systems
Feb. 08, 2018 - Siemens today announced it has entered into an agreement to acquire Oulu, Finland-based Sarokal Test Systems Oy, a provider of innovative test solutions for fronthaul networks that are comprised of links between the centralized radio controllers and the radio heads (or masts) at the "edge" of a cellular ... -
Samsung Strengthens its Foundry Customer Support with New SAFE Foundry Ecosystem Program
Jan. 25, 2018 - Samsung Electronics Co., Ltd., a world leader in advanced semiconductor technology, has announced today its continued commitment to first-pass silicon success for its foundry customers’ chip designs by launching the Samsung Advanced Foundry Ecosystem (SAFETM) program. -
Thalia expands with new analog design engineering facility
Jan. 22, 2018 - Thalia Design Automation today announced a significant expansion of its analog design engineering capabilities, with the opening of a new engineering center in Hyderabad, India. -
Andes Announces Advanced SoC Development Environments for V5 AndesCore N25 and NX25 Processors with Tool Partners
Nov. 20, 2017 - Andes Technology today announces the partnership with the world-class tools vendors including Imperas, Lauterbach, Mentor, a Siemens Business, and UltraSoC (in alphabetical order) to bring their system-on-chip (SoC) development environments to Andes V5 processors and the RISC-V community. -
Faraday Unveils M1+ Library with Enhanced Routability on UMC 28HPC Process
Nov. 16, 2017 - Faraday Technology today introduced its M1+ standard cell library on UMC 28HPC process. This optimized M1+ library supports the essential multi-track cells (7T/9T/12T), multi-Vt cells (LVT/RVT/HVT), and Faraday low-power PowerSlash™ kit to build the best portfolio of power, performance, and area metrics ... -
Global Unichip Achieves Critical ISO 13485:2016 Certification for Medical Device Components
Nov. 25, 2017 - GUC today announced the achievement of highly coveted ISO 13485:2016 certification, which make GUC the first and only ASIC company to meet these demanding standards and will strengthen qualities of medical IC design and manufacturing services. -
Open-Silicon to Demonstrate its High Bandwidth Memory (HBM2) IP Subsystem Solution for High Performance Computing and Networking Applications and Showcase its IoT Gateway SoC Reference Design for Smart City Applications at ARM TechCon 2017
Oct. 16, 2017 - Open-Silicon, a system-optimized ASIC solutions provider, will be exhibiting at ARM TechCon 2017. The company will demonstrate its IoT Edge SoC Platform Solution, IoT Gateway SoC Reference Design and Comprehensive High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in TSMC 16nm FF+. -
Samsung Certifies Synopsys Design Platform for 28nm FD-SOI Process Technology
Sep. 25, 2017 - Synopsys today announced that the Synopsys Design Platform has been fully certified for use on Samsung Foundry's 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and a comprehensive reference flow, compatible with Synopsys' Lynx Design System, containing scripts, design methodologies and ... -
Intel Custom Foundry Certifies Synopsys Design Platform for Intel's 22nm FinFET Low Power Process Technology
Sep. 19, 2017 - -
AFuzion and HDL Design House Joint Webinar: Optimizing DO-254: October 4, 2017, 4 pm CEST
Sep. 19, 2017 - AFuzion and HDL Design House invite you to join the free October 4, 2017 webinar on DO-254 optimization techniques including DO-254 requirements, mistakes, best practices, and use of random verification and UVM methodology. -
Sidense and Intellitech collaborate on Electronic Chip IDs, anti-counterfeiting and semiconductor security for Secure Supply Chain Enablement
Sep. 12, 2017 - -
Open-Silicon Completes Successful Silicon Validation of High Bandwidth Memory (HBM2) IP Subsystem Solution
Sep. 12, 2017 - Open-Silicon, a system-optimized ASIC solution provider, today announced it has successfully completed silicon validation of its High Bandwidth Memory (HBM2) IP subsystem in TSMC’s 16nm FinFET technology in combination with TSMC’s CoWoS® 2.5D silicon interposer technology and HBM2 memory. -
Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
Sep. 11, 2017 - Cadence today announced its collaboration with TSMC to advance 7nm FinFET Plus design innovation for mobile and high-performance computing (HPC) platforms. -
Synopsys' IC Compiler II Completes Certification for TSMC's 12-nm Process Technology
Sep. 11, 2017 - Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified IC Compiler™ II place-and-route system and Synopsys Design Platform for the V1.0 production of its latest 12-nanometer (nm) FinFET process technology. -
Truechip-Moving Towards 10 Years of Successfulness
Jul. 27, 2017 - Next Year in 2018, Truechip -The Verification IP specialist, would be celebrating 10 years of continued successfulness. Truechip’s completing 10 years would be a significant milestone for the company. -
Cadence Genus Synthesis Solution Enables Toshiba to Complete a Successful ASIC Tapeout with a 2X Logic Synthesis Runtime Improvement
Jul. 20, 2017 - Cadence today announced that Toshiba Electronic Devices & Storage Corporation used the Cadence® Genus™ Synthesis Solution to complete a successful ASIC design tapeout. -
Mentor Adds Veloce Strato Emulation Platform Software to Mentor Safe ISO 26262 Qualification Program
Jul. 20, 2017 - Mentor, a Siemens business, announces that independent compliance firm SGS-TÜV Saar has certified the ISO 26262 compliance of tool qualification reports for key software elements of its groundbreaking new Veloce® Strato™ emulation platform. -
Veriest Solutions and CEVA Collaborate for Neural Network Signal Processing IP Project
Jul. 13, 2017 - Veriest Solutions, a leading VLSI Design Services house, announced that it successfully completed a project with CEVA for the development of a complex neural network signal processing IP. -
eASIC Recognizes Growth in Demand From China and Establishes eASIC Shenzhen WFOE
Jun. 28, 2017 - eASIC, a fabless semiconductor company that delivers a custom integrated circuit (IC) platform (eASIC Platform), today announced the establishment of eASIC (Shenzhen) Technology Services Co. Ltd., a wholly foreign owned enterprise (WFOE) in Shenzen, China. -
ArterisIP and ResilTech Announce Strategic Partnership to Facilitate ISO 26262 Compliance for Complex Autonomous Automotive Systems
Jun. 20, 2017 - ArterisIP and ResilTech S.R.L. today announced a strategic partnership to help semiconductor design teams efficiently validate ISO26262 functional safety levels for automotive systems-on-chip. -
Truechip Collaborates with OmniPhy for Verification of PCIe Gen4 IP solution
Jun. 19, 2017 - Truechip Solutions, the Verification IP specialist and OmniPhy, a leading mixed-signal semiconductor IP company, today announced association for collaborative verification of PCIe Gen 4. The two companies enter into a partnership to provide the customers a solution that is comprehensively tested and ...