D&R Headline News | Most Popular | SoC News Alerts | |

IP / SOC Products News

• UMC adds open-source processor to flow (Tuesday Sep. 27, 2005)
  Semiconductor foundry United Microelectronics Corp. has added use of an open source 32-bit Sparc processor to a low-power reference design flow for its 130-nm manufacturing process
  
  
• Embeddia first Silicon IP for Digital Cable IP successfully introduced in the market (Tuesday Sep. 27, 2005)
  Providing Field-proven Silicon IP for Digital Cable TV reception
  
  
• Embeddia to reveal its DVB-T and DVB-H IP product family offering (Tuesday Sep. 27, 2005)
  Introducing innovative DVB-T Silicon IP (SIP) solution
  
  
• Wipro demonstrates Video transfer over UWB: Announces Development of Device IP based on Certified Wireless USB (Monday Sep. 26, 2005)
  With Wipro’s proven WiMedia MAC Intellectual Property core and third party PHY and RF modules, this demonstration features video being streamed between two laptops using the UWB protocol as per the WiMedia Alliance’s Common Radio Platform
  
  
• Renesas Technology Develops Capacitorless Twin-Transistor RAM, Enabling Faster, More Power-efficient Embedded Memory for SoC Devices (Monday Sep. 26, 2005)
  For 65nm and later-generation processes, the advanced memory has achieved fast operation (250MHz) and low active power (148mW) in a 2Mbit test chip
  
  
• Synopsys and Alereon Demonstrate Interoperability for Certified Wireless USB Technology (Monday Sep. 26, 2005)
  Testing Conducted With Synopsys' Wireless USB Device Controller IP and Alereon's WiMedia Ultra-Wideband PHY
  
  
• Synopsys Announces Industry's First Wireless USB Device Controller IP Based on the Certified Wireless USB Specification (Monday Sep. 26, 2005)
  Early IP Availability From Synopsys Drives Wireless USB Integration Into Next Generation SoCs
  
  
• Synopsys Announces Low Power PHY IP for PCI Express, XAUI and SATA (Monday Sep. 26, 2005)
  Mixed -Signal IP Complements Synopsys' Market-Leading Portfolio of Serial Interface Controllers
  
  
• Synopsys and Realtek Collaborate to Provide Interoperable IP Solution for Certified Wireless USB Technology (Monday Sep. 26, 2005)
  Companies Lead Industry With Hardware and Software Interoperability Testing
  
  
• K-Micro Introduces MIPS32(R) 24Kf(TM) Core-Based Computing Subsystem for SoCs (Monday Sep. 26, 2005)
  Ideally Suited for High-Volume Applications Needing Computing, Including PON ONU/OLT, Set-Top Boxes, Printers, Routers, and Storage Devices
  
  
• WISchip Rolls Out High-Definition Audio/Video System-On-Chip Decoder for Next-Generation Consumer Electronics (Monday Sep. 26, 2005)
  Single-Chip DeCypher 8100 Decodes H.264 (AVC), VC-1, and MPEG-1/2/4 Formats; Integrates Digital Rights Management and Networking Functionality
  
  
• Ziptronix Produces World's First Three-Dimensional System-on-Chip (Monday Sep. 26, 2005)
  Technological milestone proves benefits of ZiROC(R) bonding for 3D IC fabrication
  
  
• True Circuits Introduces New Line of High Resolution Clock Generator PLLs (Friday Sep. 23, 2005)
  Ideal for System Clock Generation, Built-in Frequency Margin Testing, SERDES and Video Clock Applications
  
  
• STMicroelectronics Publishes Certified EEMBC Results for VLIW Core Used in High Performance Embedded Consumer Applications (Thursday Sep. 22, 2005)
  ST231 processor core is ECL-certified and is designed into ST's SoC products for set-top box and DVR applications
  
  
• STMicroelectronics and Synopsys Demonstrate Interoperability of Their SATA IP Cores for 90nm Technology (Thursday Sep. 22, 2005)
  The joint ST and Synopsys solution for SATA is fully compliant with the current version of the SATA Integrated Specification Revision 2.5, including support for the latest features such as Native Command Queuing (NCQ) and 3Gbps (gigabits per second) opera
  
  
• Synopsys Speeds Development of High Performance Designs With AMBA 3 AXI Synthesizable IP in DesignWare Library (Wednesday Sep. 21, 2005)
  Addition Enables Easy Adoption of AMBA 3 AXI Protocol with Automated Subsystem Assembly and Comprehensive Set of Synthesizable and Verification IP
  
  
• Intrinsix Expands Sigma-Delta Data Converter IP Offerings (Wednesday Sep. 21, 2005)
  The Intrinsix Sigma-Delta architecture is designed to leverage standard CMOS technologies (90-250nm) from vendors such as TSMC, UMC, SMIC and others
  
  
• Digital Core Design (DCD) Announces New SPI Serial Peripheral Interface IP Cores (Tuesday Sep. 20, 2005)
  The Intellectual Property (IP) provider - Digital Core Design (DCD) today has announced the release of the DSPI_FIFO and DSPIS IP Cores
  
  
• Xilinx Bolsters Automotive Solution Offerings with First FPGA IP for Controller Area Networks (Monday Sep. 19, 2005)
  New addition to Xilinx LogiCORE library supports critical CAN IP protocol - delivers more flexibility and functionality to XA automotive PLDs
  
  
• Imagination Technologies' Vigo Mobile TV IP Platform (Friday Sep. 09, 2005)
  Single Baseband Solution Supporting Multiple Mobile TV Standards
  
  
• Gaisler Research AB launches the LEON3 processor as a standard component using the space qualified and radiation tolerant Actel RTAX2000S FPGA (Thursday Sep. 08, 2005)
  The fault tolerant LEON3 processor in combination with the recently qualified radiation tolerant ACTEL RTAX2000S FPGA will present a competitive alternative to the processors currently used by the space industry
  
  
• Xilinx And 4i2i Demonstrate Industry's First High Definition H.264/AVC Encoder Available In A Single FPGA (Wednesday Sep. 07, 2005)
  Virtex and Spartan family of FPGAs provides the performance and flexibility required in H.264 Video Encoding
  
  
• SafeNet to Launch Unique Enterprise Security Processor at Industry Conferences (Tuesday Sep. 06, 2005)
  SafeNet to Announce the OEM Product at Embedded Systems Boston and Linley Group Seminar
  
  
• Hantro Enables SDTV Resolution Video Capture for Mobile Handsets (Tuesday Sep. 06, 2005)
  Multi-format encoder design for wireless IC’s heralds the future of mobile video
  
  
• Altera & Commsonic Plan First Complete Multi-Channel FPGA-Based Universal Cable Modulator (Tuesday Sep. 06, 2005)
  Commsonic Broadcast Solutions Optimized for Altera’s Stratix II and Cyclone II FPGAs to be Demonstrated at IBC2005
  
  
• MIPS Technologies Expands Hard IP Core Family with High Performance Cores for Budget-Conscious SoC Designers (Tuesday Sep. 06, 2005)
  MIPS32® 24Kc™ and MIPS32 4KEc® Hard Cores Deliver Cost and Time-to-Market Benefits
  
  
• Chipidea's 0.13µm Low Power I&Q ADC designed for DVB-H/DMB systems excels in Silicon (Monday Sep. 05, 2005)
  This is an excellent Analog-to-Digital interface for receivers in portable systems, such as PDAs, phones, and PMPs
  
  
• Tallika announces immediate availability of broad array of IPSEC Cores (Monday Sep. 05, 2005)
  These IPSEC cores are fully compliant with IETF RFC 2401 and provide automatic processing of IPV4 packets with IP option headers
  
  
• LTRIM 10-bit A-to-D IP Block Ideal for Low-power, Muxed Input Apps (Thursday Sep. 01, 2005)
  LTRIM today announced the LTR9200-T18, a 10-bit, low-power, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) Intellectual Property (IP) block
  
  
• SOISIC Announces Semiconductor Industry's First Silicon- Proven 90nm High-Speed Silicon-On-Insulator Design Kit (Tuesday Aug. 30, 2005)
  SOISIC design kit is silicon-proven on Freescale Semiconductor’s advanced 90nm SOI process technology