The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 2.0 specification. Forward Error Correction ...

Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1Gbps, Display Stream Compression ...

Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1 Gbps. The highly integrated ...

The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development, shorten time to market, and reduce design ...

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the necessary logic to implement and verify ...

The HDMI V2.1 Tx provides a complete single-link HDMI transmitter function complies with HDMI specification version 2.1 It consists of two modules, a physical layer and a link module. The PHY ...

Display Port Transmitter core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DISPLAY ...

The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel. In an ASSP, ASIC, or FPGA, typically, ...

Display Port Receiver core is compliant with Display Port version 2.0 specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. DISPLAY PORT ...

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide designers with a robust, standards-compliant implementation ...

The first IP for PCIe 3.1 with L1 sub-states support The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising ...

Low-power, long-reach, multi-protocol PHY for PCIe 4.0 The Cadence® 10Gbps multi-protocol PHY IP provides a flexible PHY IP that simplifies the design process without compromising performance, ...

FEC RS (198,194) Decoder core is compliant with standard VESA DisplayPort version 2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (198,194) ...

FEC RS (198,194) Encoder core is compliant with standard VESA DisplayPort version 2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC RS (198,194) ...

FEC RS (254,250) Decoder core is compliant with standard VESA DisplayPort version 1.4/2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC ...

FEC RS (254,250) Encoder core is compliant with standard VESA DisplayPort version 1.4/2.0. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. FEC ...

USB TYPE C interface provides full support for the USB TYPE C synchronous serial interface, compatible with USB 3.0/2.0 and 1.0 specifications. Through its USB TYPE C compatibility, it provides ...