The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0 transceiver for usage with hosts, devices, ...

The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the USB3 PIPE interface. The USB 3.0 SSIC adapter is compliant ...

The Arasan Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses Arasan’s MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the USB3 PIPE interface. The Arasan USB 3.0 ...

INNOSILICON M-PHY implements MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system ...

The USB 3.0 SSIC controller is a highly configurable core and implements the USB 3.0 SSIC functionality that can be interfaced with third party M-PHY's. The SSIC Controller core is architected ...