Arteris FlexNoC Physical interconnect fabric IP is the first physically-aware commercial network-on-chip IP. It builds upon the already layout-friendly FlexNoC IP to shorten the time required for timing closure, physical synthesis and place and route (SP&R).
FlexNoC Physical IP includes all the features of the industry-standard FlexNoC interconnect IP. In addition, it uses information from the SoC interconnect architecture, SoC floorplan, and semiconductor process technology to both accelerate timing closure and improve QoR by using less slack to meet timing, further reducing SoC silicon area and improving performance.
- Saves time: Reduces or eliminates excessive P&R iterations
- To resolve timing closure errors on long paths, SoC designers often have to iterate over multiple P&R runs, which can take weeks. Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of timing closure issues during layout.
- Eliminates trial-and-error timing closure with automated pipeline configuration
- By analyzing the interconnect IP in the front-end design phase and automatically configuring pipeline stages as appropriate, the front-end teams hand over to the back-end team a netlist that will close timing by design.
- Optimizes Quality-of-Results (QoR)
- SoC teams often over-design their chips in the front-end stage to avoid timing problems in the back-end. FlexNoC Physical IP intelligently estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve desired frequencies, while also minimizing latencies and power consumption.
- Separates the FlexNoC interconnect physical IP from the rest of the SoC
- FlexNoC Physical offers features to separate the interconnect IP at the physical level the same way that it allows such isolation at the architectural level. Users can now generate interconnect floorplan outlines and treat the interconnect as a separate IP to be independently placed and routed by itself. Such a separation simplifies the job of the layout team.
Block Diagram of the FlexNoC Physical Interconnect IP IP Core