The USB 2.0 HS FS Function Controller provides a USB function controller that has been certified compliant with the USB 2.0 specification for high/full-speed (480/12 Mbps) functions. The core is user-configurable for up to 15 IN endpoints and/or up to 15 OUT endpoints in addition to Endpoint 0. These additional endpoints can be individually programmed for Bulk or Isochronous transfers. (Any Interrupt endpoints that are required need to be defined as Bulk because Bulk and Interrupt endpoints use the same transfer mechanisms: the difference is solely in the firmware driving the endpoint.)
Each endpoint requires a FIFO to be associated with it. The MUSBHSFC has a RAM interface for connecting to a single block of synchronous single-port RAM which is used for all the endpoint FIFOs. (The RAM block itself needs to be added by the user.) The size of the FIFO for Endpoint 0 is fixed at 64 bytes and can buffer 1 packet. The USB Controller’s FIFO interface is configurable with regard to the other endpoint FIFOs which may be from 8 to 8192 bytes in size and can buffer either 1 or 2 packets. Separate FIFOs may be associated with each endpoint: alternatively an IN endpoint and the OUT endpoint with the same Endpoint number can be configured to use the same FIFO, for example to reduce the size of RAM block needed..
The USB 2.0 HS FS Function Controller provides a USB 2.0 Transceiver Macrocell Interface (UTMI Specification version 1.05) to connect to an 8-bit high/full-speed transceiver. The design is also offered with a choice of high-level CPU interfaces. In one implementation, access to the FIFOs and the internal control/status registers is via a 16/32-bit VCI1-compatible interface. Alternatively, the USB 2.0 HS FS Function Controller can be configured to connect to a processor bus through a 32-bit AHB-compatible interface.
The USB 2.0 HS FS Function Controller provides all the USB packet encoding, decoding, checking and handshaking – interrupting the CPU only when endpoint data has been successfully transferred.
- Conforms to USB 2.0 specifications for high/full-speed functions
- Configurable for up to 15 additional IN endpoints and up to 15 additional OUT endpoints
- Configurable for FIFO sizes of 8 to 8192 bytes, including the option of dynamic FIFO sizing
- Support for high-bandwidth Isochronous transfers
- UTMI Transceiver Macrocell Interface
- Synchronous RAM Interface for FIFOs
- High-level CPU interface – either 32-bit AHB-compatible or 16/32-bit VCI-compatible
- Option of bridges to other common bus standards
- Support for DMA access to FIFOs
- Supports Suspend and Resume Signaling and Soft
- Connect/Disconnect option
- Complete Solution to accelerate your time to market
- Used for many ASICs and FPGS in past
- Very matured and highly stable IP
- Also has FPGA demo to accelerate your validation and software development
- Comes with basic software drivers
- Both Verilog and VHDL RTL files
- functional testbenches
- synthesis scripts and scan test scripts