The increasing popularity of smartphones and other multimedia enabled mobile devices along with the demand for enhanced multimedia features are pushing device manufacturers to integrate more advanced peripherals such as multi megapixel cameras and larger screens into their designs. Integrating these capabilities into mobile devices brings new challenges to the industry in terms of power, performance, time to market and overall system costs.
To address these challenges, the Mobile Industry Processor Interface (MIPI®) Alliance defines and promotes open interface specifications such as the Camera Serial Interface (CSI-2), Display Serial Interface (DSI) and UniPro which all use the MIPI D-PHY.
As a MIPI Alliance contributor and leading provider of digital and mixed-signal IP, Synopsys offers a high quality, silicon proven D-PHY solution available today in advanced technology nodes.
Low-power escape modes and ultra low-power state modes
Shutdown mode; SCAN and loopback BIST modes
Extensive access to internal programmability registers; Master, slave, Tx and Rx-only configurations
Attachable PLL for master applications; Flexible input clock reference
50% DDR output clock duty cycle
Silicon-proven, robust design available in advanced process technologies
Fully integrated hard macro
Up to 2.5 Gbps per lane
Aggregate throughput up to 10 Gbps in 4 data lanes
Supports PHY Protocol Interface (PPI)
GDSII Layout Database
Video Demo of the MIPI DPHY v1.2 RX 2 Lanes, 4 Lanes - TSMC 28HPC, HPCP 1.8V, North/South Poly Orientation